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High performance gate-all-around devices using metal induced lateral crystallization
By: Chan, P.C.H.; Chan, V.W.C.;
2000 / IEEE / 0-7803-6389-2
This item was taken from the IEEE Conference ' High performance gate-all-around devices using metal induced lateral crystallization ' Double gate or gate-all-around transistors were predicted to continue the improvement in device performance down to 0.02 /spl mu/m gate length (Wong et al., 1997; Colinge et al., 1990; Tanaka et al., 1994). In this work, a high performance gate-all-around transistor (GAT) is demonstrated. The device is fabricated from either a bulk silicon wafer or on the top of any device layers. The fabrication process uses metal-induced-lateral-crystallization (MILC) to recrystallize the amorphous silicon to form large silicon grains in the active area. Using this technique, the transistor performance is comparable to a SOI MOSFET (Jagar et al., 1999). Compared to the method of cavity etch on the buried oxide, our method provides a uniform bottom gate length. Compared to the single-gate thin film transistor (SGT) and solid phase crystallization (SPC) devices, the GAT has lower subthreshold slope, lower threshold voltage, higher transconductance, nearly double the drive current and lower off-current. The impact of channel length and width scaling is investigated.
Semiconductor Device Metallisation
Semiconductor Device Measurement
Si-sio/sub 2/-si/sub 3/n/sub 4/-sio/sub 2/-si
Metal Induced Lateral Crystallization
Double Gate Transistors
Bulk Silicon Wafer
Device Fabrication Process
Amorphous Silicon Recrystallization
Large Silicon Grain Formation
Soi Mosfet Performance
Uniform Bottom Gate Length
Single-gate Thin Film Transistor
Solid Phase Crystallization Devices
Channel Length Scaling
Channel Width Scaling