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Large-grain polysilicon MOSFET for 3-D integrated circuits

By: Mansun Chan; Chan, P.C.H.; Chan, V.W.C.;

2000 / IEEE / 0-7803-6389-2


This item was taken from the IEEE Conference ' Large-grain polysilicon MOSFET for 3-D integrated circuits ' The paper reports a large-grain polysilicon MOSFET that can be used to construct three dimensional circuits on SOI and bulk wafers. In this new technology, two layers of CMOS transistors are fabricated and separated by an insulating layer. When the devices of each layer are interconnected, a high performance 3D circuit can be realized. This results in the reduction of the interconnect length from microns to less than one micron, thus decreases the interconnect resistance and capacitance, and potentially increases the speed (Zhang et al., 1999). Moreover, if the NMOS devices are on the primary level and the PMOS devices are built on the second level, implant masking can be eliminated and the CMOS circuits can still be achieved.