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60 nm planarized ultra-thin body solid phase epitaxy MOSFETs

By: Tsu-Jae King; Bokor, J.; Subranmanian, V.; Kedzierski, J.; Peiqi Xuan; Chenming Hu;

2000 / IEEE / 0-7803-6472-4


This item was taken from the IEEE Conference ' 60 nm planarized ultra-thin body solid phase epitaxy MOSFETs ' The continuous scaling of MOSFET technology into the deep sub-micron regime poses considerable challenge to the conventional MOSFET structure. To suppress short-channel effects such as DIBL and V/sub t/ roll-off, extremely high levels of channel doping are required, but these result in increased leakage and degraded mobility. Simulation shows that the ultra-thin body MOSFET is a promising alternative structure that effectively suppresses DIBL and other short channel effects. The channel film thickness required is typically 30% of the gate length. The most difficult step for fabrication of the ultra-thin body FET is the formation of a uniform thin channel film. Oxidation and etch back have been proposed, but are limited by thickness uniformity of the starting SOI wafers and by process-induced variation. On the other hand, deposited films can be well controlled and have good uniformity, so finding ways to deposit highly uniform channel material is very plausible. Solid phase epitaxy (SPE) has been reported for fabrication of sub-100 nm devices (Subramanian et al, 1999). In SPE, the thin film is formed by lateral crystallization of an amorphous deposited silicon film, giving precise control over channel thickness. In this paper, 60 nm planarized SPEFETs with excellent performance are reported. The effect of different trench sizes is investigated. Both single sided and two sided crystallization on the channel film is also studied.