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An iterative algorithm for partitioning and scheduling of area constrained HW-SW systems
By: Chatha, K.S.; Vemuri, R.;
1999 / IEEE / 0-7695-0246-6
This item was taken from the IEEE Conference ' An iterative algorithm for partitioning and scheduling of area constrained HW-SW systems ' We present a technique for integrated partitioning and scheduling of hardware-software systems. The tool takes a task graph and area constraint as input and obtains a mapping and schedule such that the execution time is minimized. The algorithm differs from other approaches which either obtain the mapping during the partitioning stage or the scheduling stage. We use an iterative approach where the partitioner assigns the mapping of only some of the tasks and the remaining tasks are assigned by the scheduler with an objective of minimizing the execution time. The technique takes both the time and area overheads due to inter-processor and intra-processor communication into account. The effectiveness of the approach is demonstrated by the experimental results.
Hardware Software Codesign
Area Constrained Hardware Software Systems