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A modular digital VLSI architecture for stereo depth estimation in industrial applications
By: Alimonda, A.; Raffo, L.; Carta, S.M.;
1999 / IEEE / 0-7803-5471-0
Description
This item was taken from the IEEE Conference ' A modular digital VLSI architecture for stereo depth estimation in industrial applications ' In this paper a modular architecture for real time stereo depth estimation is synthesized. The elaboration is described in terms of the action of a set of sub-processors working in parallel. Such modules have been implemented using proper mechanism to reduce their complexity. Simulations on real and synthetic images are presented and real-time performance evidenced.
Related Topics
Vlsi
Digital Signal Processing Chips
Parallel Processing
Parallel Processing
Modular Digital Vlsi Architecture
Stereo Depth Estimation
Real-time Imaging
Simulation
Very Large Scale Integration
Cameras
Interpolation
Concurrent Computing
Pixel
Performance Evaluation
Intersymbol Interference
Parallel Processing
Image Resolution
Hardware Design Languages
Spatial Variables Measurement
Stereo Image Processing
Real-time Systems
Engineering
Industrial Application
