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Comparative analysis of sensing schemes for multilevel non-volatile memories
1997 / IEEE / 0-7803-4276-3
This item was taken from the IEEE Conference ' Comparative analysis of sensing schemes for multilevel non-volatile memories ' Reading multilevel non-volatile memories is a very demanding task. Three sensing techniques (the parallel scheme, the binary-serial scheme and the mixed parallel-serial scheme) are considered here. Their operation principles are described and a comparative evaluation in terms of both access time and circuit complexity is carried out. The parallel approach is the most suitable for 4-level-cell memories (2 bit per cell). The mixed approach seems to be the most attractive for a large number of programmable levels (at least 16 levels per cell). In this case, the sensing area overhead is limited to less than 1% of the memory array while access time penalty is less than 50%.
Multilevel Nonvolatile Memories
Sensing Area Overhead
Access Time Penalty
Integrated Memory Circuits
Mixed Parallel-serial Scheme