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Deriving signal constraints to accelerate sequential test generation

By: Rothweiler, S.; Gangaram, V.; Chakradhar, S.T.;

1997 / IEEE / 0-8186-7755-4

Description

This item was taken from the IEEE Periodical ' Deriving signal constraints to accelerate sequential test generation ' We propose a new method to significantly accelerate sequential test generation algorithms. The main idea is to accurately compute signal constraints for large sequential circuits and use these constraints effectively during deterministic sequential test generation. Our signal constraint computation technique is based on three key Ideas: (1) unlike prior techniques (which compute line probabilities assuming only a 0 or 1 logic value for any signal), line probabilities are computed by allowing signals to assume values other than 0 or 1, (2) line justification techniques are employed to update line probabilities, and (3) symbolic simulation is iteratively used in conjunction with line probability computation and line justification to refine the set of values that a signal can assume. Experimental results on several large production and benchmark sequential circuits show that our technique results in a significant reduction (more than 50%) in the test generation time. This reduction is achieved without compromising the fault coverage that can be obtained by the base system. By incorporating our technique into the base system, we obtained higher fault coverage using fewer CPU seconds for a majority of example sequential circuits.