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# n-dimensional processor arrays with optical dBuses

## By: Lee, K.Y.; Guoping Liu; Jordan, H.F.;

1995 / IEEE / 0-8186-7101-7

### Description

This item was taken from the IEEE Periodical ' n-dimensional processor arrays with optical dBuses ' dBus-array(k,n) is an n-dimensional processor array of k/sup n/ nodes connected via k/sup n-1/ dBuses. A dBus is a unidirectional bus which receives signals from a set of n nodes (input set), and transmits signals to a different set of n nodes (output set). Two optical implementations of the dBus-array(k,n) are discussed. One implementation uses the wavelength division multiplexing as in the wavelength division multiple access channel hypercube WMCH (P.W. Dowd, 1992). WMCH(k,n) and dBus-array(k,n) have the same diameter and about the same average internode distance, while the dBus-array requires only one tunable transmitter/receiver per node. Compared to n tunable transmitters/receivers per node for the WMCH. The other implementation uses one fixed wavelength transmitter/receiver per node and the dilated slipped banyan switching network (DSB) (R.A. Thompson, 1991) to combine the time division and wavelength division multiplexing (G. Lin et al., 1994).

**Related Topics**

System Buses

Optical Interconnections

Wavelength Division Multiplexing

Time Division Multiplexing

N-dimensional Processor Arrays

Optical Dbuses

Dbus-array

Unidirectional Bus

Optical Implementations

Wavelength Division Multiplexing

Wmch

Average Internode Distance

Tunable Transmitter/receiver

Fixed Wavelength Transmitter/receiver

Dilated Slipped Banyan Switching Network

Dsb

Optical Arrays

Optical Transmitters

Hypercubes

Optical Receivers

Wavelength Division Multiplexing

Network Topology

Mathematics

Computer Science

Multiprocessor Interconnection

Wavelength Routing

Parallel Architectures

Hypercube Networks

Time Division Multiplexing

Engineering

Wavelength Division Multiple Access Channel Hypercube