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Serendipitous SEU hardening of resistive load SRAMs

By: Hansel, S.J.; Pinkerton, S.D.; Kirshman, J.F.; Koga, R.; Crain, W.R.; Crawford, K.B.;

1995 / IEEE / 0-7803-3093-5


This item was taken from the IEEE Periodical ' Serendipitous SEU hardening of resistive load SRAMs ' High and low resistive load versions of Micron Technology's MT5C1008C(128 K/spl times/8) and MT5C2561C(256 K/spl times/1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load A substantially larger number of multiple-bit errors were observed for the low resistive load SRAMs, which also exhibited a ""1""/spl rarr/""0"" to ""0""/spl rarr/""1"" bit error ratio close to unity; in contrast, the high resistive load devices displayed a pronounced error bit polarity effect. Two distinct upset mechanisms are proposed to account for these observations.