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The correlation between latch-up phenomenon and other failure mechanisms

By: Morgan, I.; Mahanpour, M.;

1995 / IEEE / 1-878303-59-7


This item was taken from the IEEE Periodical ' The correlation between latch-up phenomenon and other failure mechanisms ' A previous study by L. G. Henry et al. (see Proceedings 20th ISTFA, Los Angeles, p. 117-26, Nov. 1994) considered in detail an early die revision of a CMOS logic product fabricated using an N-well technology, that showed a higher than expected rate of EOS failure during burn-in and for customer field returns. It was shown that the use of a specific laboratory model simulator can most often replicate a failure signature, i.e., a unique damage morphology and die location associated with a real product failure. A ""nondestructive"" failure signature induced by Transient Latch-Up (TLU) was described and is studied here in more detail. Five different failure mechanisms were found in the area where Latch-Up (LU) was located by emission microscopy: fusing of the V/sub cc/ metal-bus, metal-metal shorts, metal-poly shorts, gate oxide defects, and a carrier storage effect. This study shows that 90% of all defects identified were within or in close proximity to the latch-up sites. These several failure mechanisms and their relation to LU are discussed.