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Functional comparison of logic designs for VLSI circuits
By: Trevillyan, L.H.; Berman, C.L.;
1989 / IEEE / 0-8186-1986-4
This item was taken from the IEEE Periodical ' Functional comparison of logic designs for VLSI circuits ' A method is described for circuit equivalence which proceeds by reducing the question of whether two circuits are equivalent to a number of a more easily answered questions concerning the equivalence of smaller, related circuits. The primary technical contribution is a technique for discovering internal equivalences and using them to show the equivalence of the outputs. The method involves the use of signatures to reduce the number of potentially equivalent signals, and the use of the min-cut algorithm to reduce the original problem to related problems with fewer independent inputs. The method can be used to extend the power of any given equivalence checking algorithm. The authors report the result of experiments evaluating their technique.<
Equivalence Checking Algorithm
Very Large Scale Integration