Your Search Results

Use this resource - and many more! - in your textbook!

AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

Technology Adaptation in Logic Synthesis

By: Nix, T.A.; Brand, D.; Trevillyan, L.H.; Joyner, W.H.; Gundersen, S.C.;

1986 / IEEE / 0-8186-0702-5

Description

This item was taken from the IEEE Periodical ' Technology Adaptation in Logic Synthesis ' Systems which synthesize logic implementations from specifications have moved, under the pressure of production requirements, from Boolean minimizers to procedures attempting to satisfy a wider range of criteria. Gate or cell count, taken as a measure of area, continues to be a major factor in design acceptability, but timing constraints, testability, wirability, and efficient use of available primitives are important as well. Additional information, such as ""don't care"" conditions, can be used to improve the design quality. This paper describes how these requirements are specified to and enforced by the Logic Synthesis System (LSS), a tool which has been used in production on gate array chips. Trade-offs between varying requirements, and their effect on the logic produced, are discussed and illustrated with a standard set of examples.