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Bringing NoCs to 65 nm

By: Angiolini, F.; Pullini, A.; Benini, L.; De Micheli, G.; Atienza, D.; Murali, S.;

2007 / IEEE


This item was taken from the IEEE Periodical ' Bringing NoCs to 65 nm ' Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of NoC-based interconnect design in nanometer CMOS. The experimental results from fully working 65-nm NoC designs and a detailed scalability analysis are presented. The network on chip (NoC) is a promising solution to the scalability problem. NoCs build upon improvements in bus architecture-for example, in terms of topology design.