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Hybrid-orientation technology (HOT): opportunities and challenges

By: Min Yang; Meikei Ieong; Fischetti, M.V.; Burns, L.E.; Ott, J.A.; Chan, K.K.; Chan, V.W.C.; Chou, A.I.; Stathis, J.H.; Fried, D.M.; Shi, L.; Gusev, E.;

2006 / IEEE


This item was taken from the IEEE Periodical ' Hybrid-orientation technology (HOT): opportunities and challenges ' At the onset of innovative device structures intended to extend the roadmap for silicon CMOS, many techniques have been investigated to improve carrier mobility in silicon MOSFETs. A novel planar silicon CMOS structure, seeking optimized surface orientation, and hence carrier mobilities for both nFETs and pFETs, emerged. Hybrid-orientation technology provides nFETs on (100) surface orientation and pFETs on [110] surface orientation through wafer bonding and silicon selective epitaxy. The fabrication processes and device characteristics are reviewed in this paper.