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Fabrication of raised S/D gate-all-around transistor and gate misalignment analysis

By: Chan, V.W.C.; Chan, P.C.H.; Chunshan Yin;

2003 / IEEE

Description

This item was taken from the IEEE Periodical ' Fabrication of raised S/D gate-all-around transistor and gate misalignment analysis ' In this letter, we present the implementation of a new raised source/drain (S/D) gate-all-around transistor (GAT). The device is fabricated on a bulk silicon wafer using a technique known as metal-induced-lateral-crystallization (MILC). Compared to conventional single gate MOSFETs, the GAT shows a smaller subthreshold-slope (SS), reduced drain-induced barrier lowering (DIBL), and almost doubled (187%) drive current. Gate misalignment is briefly studied using this novel device. It is found that the SS, DIBL, and drive current will degrade abruptly when gate misalignment is larger than 17% of gate length.