Use this resource - and many more! - in your textbook!
AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.
Performance and power effectiveness in embedded processors - customizable partitioned caches
By: Petrov, P.; Orailoglu, A.;
2001 / IEEE
This item was taken from the IEEE Periodical ' Performance and power effectiveness in embedded processors - customizable partitioned caches ' This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural features of modern embedded processors. The automated methodology for. customizing the processor microarchitecture that we propose results in increased performance, reduced power consumption and improved determinism of critical system parts while the fixed design ensures processor standardization. The resulting improvements help to enlarge the significant role of embedded processors in modern hardware-software codesign techniques by leading to increased processor utilization and reduced hardware cost. A novel methodology for static analysis and a microarchitecturally field-reprogrammable implementation of a customizable cache controller that implements a partitioned cache structure is proposed. Partitioning the load/store instructions eliminates cache interference; hence, precise knowledge about the hit/miss behavior of the references within each partition becomes available, resulting in significant reduction in tag reads and comparisons. Moreover, eliminating cache interference naturally leads to a significant reduction in the miss rate. The paper presents an algorithm for defining cache partitions, hardware support for customizable cache partitions, and a set of experimental results. The experimental results indicate significant improvements in both power consumption and miss rate.
Application Specific Integrated Circuits
Miss Rate Improvement
Application-specific Customization Technique
Power Consumption Reduction
Microarchitecturally Field-reprogrammable Implementation
Customizable Cache Controller
Partitioned Cache Structure
Load/store Instructions Partitioning
Cache Interference Elimination
Field Programmable Gate Arrays
Computing And Processing
Components, Circuits, Devices And Systems