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Three-dimensional CMOS SOI integrated circuit using high-temperature metal-induced lateral crystallization

By: Mansun Chan; Chan, P.C.H.; Chan, V.W.C.;

2001 / IEEE

Description

This item was taken from the IEEE Periodical ' Three-dimensional CMOS SOI integrated circuit using high-temperature metal-induced lateral crystallization ' A three-dimensional (3-D) CMOS integrated circuit was fabricated based on the conventional CMOS SOI technology. The first layer of transistors was formed on the SOI. The second layer of transistors was built on large-grain polysilicon-on-insulator (LPSOI). The recrystallized film was formed by the recrystallization of amorphous silicon using metal-induced lateral crystallization (MILC). The devices from the lower and upper layers were characterized and the result indicated that the SOI and LPSOI devices have similar electrical characteristics. The 3-D circuit design and layout considerations are introduced. The 3-D CMOS inverters were demonstrated with p-channel devices stacking over the n-channel ones. The ring-oscillator showed that the 3-D circuit has 30% reduction in the layout area and it operated at power supply as low as 0.5 V. The lower propagation delay and load capacitance suggest that 3-D circuit has higher performance than the conventional two-dimensional (2-D) circuit.