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Distributed ESD protection for high-speed integrated circuits

By: Morgan, I.; Maloney, T.J.; Kleveland, B.; Wong, S.S.; Lee, T.H.; Madden, L.;

2000 / IEEE


This item was taken from the IEEE Periodical ' Distributed ESD protection for high-speed integrated circuits ' Conventional ESD guidelines dictate a large protection device close to the pad. The resulting capacitive load causes a severe impedance mismatch and bandwidth degradation. A distributed ESD protection scheme is proposed to enable a low-loss impedance-matched transition from the package to the chip. A simple resistive model adequately predicts the ESD behavior under stress according to the charged device and human body models. The large area of the distributed ESD scheme could limit its application to designs such as distributed amplifiers, rf transceivers, A/D converters, and serial links with only a few dedicated high-speed interfaces. The distributed ESD protection is compatible with high-speed layout guidelines, requiring only low-loss transmission lines in addition to a conventional ESD device.