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Contention solver for a superconducting packet switch

By: Kominami, S.; Hosoya, M.; Nishino, T.; Hioe, W.;

1997 / IEEE


This item was taken from the IEEE Periodical ' Contention solver for a superconducting packet switch ' The paper describes the architecture of a contention solver (CS) to be used in a superconducting packet switch prototype, and the design and tests of 2/spl times/2 switching elements which compose the CS. The contention solver is based on a Batcher sorter, in which switching elements check for contention between input packets. A priority port is used to guarantee correct operation of the sorter even if a packet is invalidated during the sorting process. A 2/spl times/2 CS switching element with 2-bit data-width was designed in dual-rail logic. It was fabricated using three-junction SQUID gates by a standard Nb tri-layer process, and consists of 102 OR-equivalent gates in an area of 1.2 mm x 1.8 mm. Its correct operation was confirmed completely.