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Balancing contention and synchronization on the Intel Paragon
By: Nicol, D.M.; Bokhari, S.H.;
1997 / IEEE
This item was taken from the IEEE Periodical ' Balancing contention and synchronization on the Intel Paragon ' The authors show how synchronization time can be reduced by increasing contention. Their experience indicates that, despite improvements in interprocessor communication hardware, parallel algorithm designers still need to take topology into account to obtain high performance.
Software Performance Evaluation
Multiprocessor Interconnection Networks
Parallel Algorithm Design
Algorithm Design And Analysis
Integrated Circuit Interconnections
Power Engineering And Energy
Distributed Memory Systems
Computing And Processing