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Demonstration of a deflection routing 2*2 photonic switch for computer interconnects

By: Blumenthal, D.J.; Sauer, J.R.; Feuerstein, R.J.; Ma, J.; Chen, K.Y.;

1992 / IEEE

Description

This item was taken from the IEEE Periodical ' Demonstration of a deflection routing 2*2 photonic switch for computer interconnects ' The first reported demonstration of a 2*2 self-routing photonic switch is presented. Output port contention is handled using a deflection routing protocol implemented by a pipelined electrooptic processor. Routing and data bits are encoded in separated multiwavelength channels occupying only a portion of a full packet period. This encoding technique accommodates timing uncertainty, reduces the effective electronic processing rate at the switching node, and maintains a high-link throughput. In the authors' single-node demonstration. The packet header contains two address bits plus one priority bit for contention resolution, and one packet payload is represented by a single bit. Control information is encoded at 830 nm with 3.6 nm channel spacing and data at 1300 nm. The switch, implemented with longer wavelength transmission bands, is an efficient building block for large-scale, wide-area, high-capacity networks.<>