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A comprehensive CAD system for high-performance 300 K-circuit ASIC logic chips

By: Carrig, K.M.; Bassett, R.W.; Abato, R.P.; Panner, J.H.; Sehr, T.W.; Hathaway, D.J.; Gillis, P.S.;

1991 / IEEE

Description

This item was taken from the IEEE Periodical ' A comprehensive CAD system for high-performance 300 K-circuit ASIC logic chips ' A computer-aided design (CAD) system has been developed to support design of CMOS application-specific integrated circuit (ASIC) logic chips containing more than 300 K equivalent two-input NANDs with 180-ps typical gate delays. The underlying technology is a 0.8- mu m, four-level-metal, single-poly CMOS process, with a 0.45- mu m nominal effective channel length and 180-ps typical gate delay. Both standard-cell and gate-array circuit libraries are provided, including fixed and growable memory macros. Key new system features are described in the areas of high-level design and synthesis, delay calculation and timing analysis, timing guidance to physical design, physical design, clock construction, and test generation. Early processing results are reported for several test chips, including a 9.7-mm 2-million-transistor chip and a 14.5-mm 300 K-equivalent-gate chip.<>