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A 4-Mbit DRAM with trench-transistor cell

By: Wang, C.; Womack, R.H.; Shah, A.H.; Chatterjee, P.K.; Tran, B.; Pilch, C.J.; Malhi, S.D.S.; Bordelon, D.M.; Richardson, W.F.; Pollack, G.P.; Banerjee, S.K.; Elahy, M.; Davis, H.E.; Shichijo, H.; Gallia, J.D.;

1986 / IEEE


This item was taken from the IEEE Periodical ' A 4-Mbit DRAM with trench-transistor cell ' An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.