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Author: Zorian, Y.

Results

A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs
2012 / IEEE
By: Shoukourian, S.; Harutyunyan, G.; Zorian, Y.; Vardanian, V.;
Message From the Steering Committee
2012 / IEEE
By: Gulak, G.; Gupta, R.; Setti, G.; Zorian, Y.;
Generic BIST architecture for testing of content addressable memories
2011 / IEEE / 978-1-4577-1056-8
By: Harutyunyan, G.; Grigoryan, H.; Zorian, Y.; Vardanian, V.; Shoukourian, S.;
A Robust Solution for Embedded Memory Test and Repair
2011 / IEEE / 978-1-4577-1984-4
By: Vardanian, V.; Shoukourian, S.; Harutyunyan, G.; Darbinyan, K.; Zorian, Y.;
Design for test and reliability in ultimate CMOS
2012 / IEEE / 978-1-4577-2145-8
By: Raychowdhury, A.; Khellah, M.; Shih-Lien Lu; Tschanz, J.; Tokunaga, C.; Bowman, K.; Karnik, T.; Zorian, Y.; Zergainoh, N.-E.; Anghel, L.; Nicolaidis, M.; Avresky, D.; De, V.; Kulkarni, J.;
An effective solution for building memory BIST infrastructure based on fault periodicity
2013 / IEEE
By: Vardanian, V.; Shoukourian, S.; Harutyunyan, G.; Zorian, Y.;
Message from the LATS2015 Chairs
2015 / IEEE
By: Agrawal, V.; Bolzani Pohls, L.; Zorian, Y.; Champac, V.;
Extending fault periodicity table for testing faults in memories under 20nm
2014 / IEEE
By: Harutyunyan, G.; Zorian, Y.; Vardanian, V.; Shoukourian, S.;
Test and Repair Methodology for FinFET-Based Memories
2015 / IEEE
By: Harutyunyan, G.; Zorian, Y.; Tshagharyan, G.;
Guest Editors' Introduction: Highlights of the 50th DAC
2014 / IEEE
By: Zorian, Y.; Hassoun, S.;
Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture
1989 / IEEE / 0-8186-1971-6
By: Jarwala, N.; Zorian, Y.;
EEODM: An effective BIST scheme for ROMs
1990 / IEEE / 0-8186-9064-X
By: Ivanov, A.; Zorian, Y.;
Computing the error escape probability in count-based compaction schemes
1990 / IEEE / 0-8186-2055-2
By: Ivanov, A.; Zorian, Y.;
Count-based BIST compaction schemes and aliasing probability computation
1992 / IEEE
By: Ivanov, A.; Zorian, Y.;
An effective BIST scheme for ROM's
1992 / IEEE
By: Ivanov, A.; Zorian, Y.;
Functional tests for arbitration SRAM-type FIFOs
1992 / IEEE / 0-8186-2985-1
By: van de Goor, A.J.; Zorian, Y.;
Fault models and tests specific for FIFO functionality
1993 / IEEE / 0-8186-4150-9
By: Zorian, Y.; van de Goor, A.J.;
A universal testability strategy for multi-chip modules based on BIST and boundary-scan
1992 / IEEE / 0-8186-3110-4
By: Zorian, Y.;
Fault models and tests for Ring Address Type FIFOs
1994 / IEEE / 0-8186-5440-6
By: Schanstra, I.; Van de Goor, A.J.; Zorian, Y.;
A structured testability approach for multi-chip modules based on BIST and boundary-scan
1994 / IEEE
By: Zorian, Y.;
A distributed BIST control scheme for complex VLSI devices
1993 / IEEE / 0-8186-3830-3
By: Zorian, Y.;
Functional tests for ring-address SRAM-type FIFOs
1994 / IEEE / 0-8186-5410-4
By: Schanstra, I.; Zorian, Y.; van de Goor, A.J.;
Selecting programmable space compactors for BIST using genetic algorithms
1994 / IEEE / 0-8186-6690-0
By: Tsuji, B.; Zorian, Y.; Ivanov, A.;
Effective march algorithms for testing single-order addressed memories
1993 / IEEE / 0-8186-3410-3
By: Zorian, Y.; van de Goor, A.;
BIST for ring-address SRAM-type FIFOs
1994 / IEEE / 0-8186-6245-X
By: van de Goor, A.J.; Zorian, Y.; Schanstra, I.;
Area versus detection latency trade-offs in self-checking memory design
1995 / IEEE / 0-8186-7039-8
By: Kebichi, O.; Nicolaidis, M.; Zorian, Y.;
Functional test for shifting-type FIFOs
1995 / IEEE / 0-8186-7039-8
By: Zorian, Y.; Schanstra, I.; van de Goor, A.J.;
PSBIST: A partial-scan based built-in self-test scheme
1993 / IEEE / 0-7803-1430-1
By: Bhawmik, S.; Zorian, Y.; Lin, C.-J.;
A method for delay fault self-testing of macrocells
1993 / IEEE / 0-7803-1430-1
By: Scholz, H.N.; Zorian, Y.; Aadsen, D.R.;
The effective use of BIST and boundary-scan in multi-chip module testing
1994 / IEEE / 0-7803-2630-X
By: Zorian, Y.;
An effective BIST scheme for carry-save and carry-propagate array multipliers
1995 / IEEE / 0-8186-7129-7
By: Gizopoulos, D.; Zorian, Y.; Paschalis, A.;
East Meets West [Guest Editors' Introduction:]
1996 / IEEE
By: Zorian, Y.; Hlavicka, J.;
Multi-chip module technology
1995 / IEEE / 0-7803-2768-3
By: Zorian, Y.;
Relay propagation scheme for testing of MCMs on large area substrates
1996 / IEEE / 0-8186-7424-5
By: Sasidhar, K.; Zorian, Y.; Chatterjee, A.;
Designing self-testable multi-chip modules
1996 / IEEE / 0-8186-7424-5
By: Bederr, H.; Zorian, Y.;
Built-in quality assurance
1994 / IEEE / 0-8186-6595-5
By: Zorian, Y.;
Multi-chip modules testing and DFT
1995 / IEEE / 0-7803-2972-4
By: Zorian, Y.; Marzouki, M.;
An effective BIST scheme for ring-address type FIFOs
1994 / IEEE / 0-7803-2103-0
By: Zorian, Y.; Schanstra, I.; Van de Goor, A.J.;
Do you practice safe test? What we found out about your habits
1994 / IEEE / 0-7803-2103-0
By: Dean, C.A.; Zorian, Y.;
An approach for designing total-dose tolerant MCMs based on current monitoring
1995 / IEEE / 0-7803-2992-9
By: Vargas, F.; Zorian, Y.; Nicolaidis, M.;
An effective BIST scheme for Booth multipliers
1995 / IEEE / 0-7803-2992-9
By: Gizopoulos, D.; Zorian, Y.; Paschalis, A.;
Programmable BIST space compactors
1996 / IEEE
By: Tsuji, B.K.; Ivanov, A.; Zorian, Y.;
Optimal multiple chain relay testing scheme for MCMs on large area substrates
1996 / IEEE / 0-7803-3541-4
By: Chatterjee, A.; Sasidhar, K.; Zorian, Y.;
On the generation of pseudo-deterministic two-patterns test sequence with LFSRs
1997 / IEEE / 0-8186-7786-4
By: Dufaza, C.; Zorian, Y.;
Fault-secure shifter design: results and implementations
1997 / IEEE / 0-8186-7786-4
By: Bederr, H.; Nicolaidis, M.; Duarte, R.O.; Zorian, Y.;
Testing Embedded Cores
1997 / IEEE
By: Walther, R.; Chandramouli, R.; Anderson, T.L.; Zorian, Y.; Dey, S.; Rajsuman, R.; Mallipeddi, C.; Hemmady, S.;
Test of RAM-based FPGA: methodology and application to the interconnect
1997 / IEEE / 0-8186-7810-0
By: Zorian, Y.; Figueras, J.; Renovell, M.;
Programmable space compaction for BIST
1993 / IEEE / 0-8186-3680-7
By: Zorian, Y.; Ivanov, A.;
Introducing core-based system design
1997 / IEEE
By: Gupta, R.K.; Zorian, Y.;
Test requirements for embedded core-based systems and IEEE P1500
1997 / IEEE / 0-7803-4209-7
By: Zorian, Y.;
An effective BIST scheme for arithmetic logic units
1997 / IEEE / 0-7803-4209-7
By: Pachalis, A.; Gizopoulos, D.; Psarakis, M.; Zorian, Y.;
Test pattern and test configuration generation methodology for the logic of RAM-based FPGA
1997 / IEEE / 0-8186-8209-4
By: Portal, J.M.; Renovell, M.; Zorian, Y.; Figueras, J.;
Testing the interconnect of RAM-based FPGAs
1998 / IEEE
By: Zorian, Y.; Figueras, J.; Portal, J.M.; Renovell, M.;
RAM-based FPGAs: a test approach for the configurable logic
1998 / IEEE / 0-8186-8359-7
By: Zorian, Y.; Figueras, J.; Portal, J.M.; Renovell, M.;
Built-in self-test with an alternating output
1998 / IEEE / 0-8186-8359-7
By: Bogue, T.; Zorian, Y.; Jurgensen, H.; Gossel, M.;
Robustly testable array multipliers under realistic sequential cell fault model
1998 / IEEE / 0-8186-8436-4
By: Psarakis, M.; Zorian, Y.; Paschalis, A.; Gizopoulos, D.;
Effective built-in self test for Booth multipliers
1998 / IEEE
By: Paschalis, A.; Gizopoulos, D.; Zorian, Y.;
System-chip test strategies
1998 / IEEE / 0-89791-964-5
By: Zorian, Y.;
SRAM-based FPGA's: testing the interconnect/logic interface
1998 / IEEE / 0-8186-8277-9
By: Portal, J.M.; Renovell, M.; Zorian, Y.; Figueras, J.;
Tutorial 3 High-level Design Validation And Test
1998 / IEEE / 1-58113-008-2
By: Dey, S.; Abraham, J.; Zorian, Y.;
Synthesis of BIST hardware for performance testing of MCM interconnections
1998 / IEEE / 1-58113-008-2
By: Zorian, Y.; Chatterjee, A.; Pendurkar, R.;
Testing embedded-core based system chips
1998 / IEEE / 0-7803-5093-6
By: Zorian, Y.; Dey, S.; Marinissen, E.J.;
A distributed BIST technique for diagnosis of MCM interconnections
1998 / IEEE / 0-7803-5093-6
By: Zorian, Y.; Chatterjee, A.; Pendurkar, R.;
SRAM-based FPGA's: testing the LUT/RAM modules
1998 / IEEE / 0-7803-5093-6
By: Renovell, M.; Zorian, Y.; Figueras, J.; Portal, J.M.;
Built in self repair for embedded high density SRAM
1998 / IEEE / 0-7803-5093-6
By: Lewandowski, J.L.; Higgins, F.P.; Pham, H.; Komoriya, G.; Zorian, Y.; Ilyoung Kim;
AD&T Roundtable: Online Test
1999 / IEEE
By: Motto, S.; Ievendel, I.; Abramovici, M.; Abraham, J.A.; Zorian, Y.; Nicolaidis, M.;
An effective BIST architecture for fast multiplier cores
1999 / IEEE / 0-7695-0078-1
By: Kranitis, N.; Gizopoulos, D.; Paschalis, A.; Zorian, Y.; Psarakis, M.;
Scaling deeper to submicron: on-line testing to the rescue
1999 / IEEE / 0-7695-0078-1
By: Nicolaidis, M.; Zorian, Y.;
Testing the configurable interconnect/logic interface of SRAM-based FPGA's
1999 / IEEE / 0-7695-0078-1
By: Figueras, J.; Portal, J.M.; Renovell, M.; Zorian, Y.;
On testing of non-isolated embedded legacy cores and their surround logic
1999 / IEEE / 0-7695-0146-X
By: Zorian, Y.; Pomeranz, I.;
An effective BIST architecture for sequential fault testing in array multipliers
1999 / IEEE / 0-7695-0146-X
By: Paschalis, A.; Gizopoulos, D.; Psarakis, M.; Zorian, Y.;
Preliminary Outline of the IEEE PI 500 Scalable Architecture for Testing Embedded Cores
1999 / IEEE / 0-7695-0146-X
By: Adham, S.; Burek, D.; Zorian, Y.; Zamfirescu, A.; Whetsel, L.; Varma, P.; Udell, J.; Stannard, D.; Ricchatti, M.; Rajsuman, R.; Rajoki, J.; Muradali, F.; Monzel, J.; Clark, C.J.; Collins, M.; Giles, G.; Sales, A.; Marinissen, E.J.; McLaurin, T.;
Challenges in testing core-based system ICs
1999 / IEEE
By: Marinissen, E.J.; Zorian, Y.;
Testing embedded-core-based system chips
1999 / IEEE
By: Zorian, Y.; Dey, S.; Marinissen, E.J.;
Testing the monster chip
1999 / IEEE
By: Zorian, Y.;
An effective built-in self-test scheme for parallel multipliers
1999 / IEEE
By: Zorian, Y.; Paschalis, A.; Gizopoulos, D.;
Testing semiconductor chips: trends and solutions
1999 / IEEE / 0-7695-0387-X
By: Zorian, Y.;
A high-level EDA environment for the automatic insertion of HD-BIST structures
1999 / IEEE / 0-7695-0390-X
By: Prinetto, P.; Chiusano, S.; Cataldo, S.; Benso, A.; Zorian, Y.;
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study
1999 / IEEE / 0-7695-0390-X
By: Figueras, J.; Portal, J.M.; Renovell, M.; Zorian, Y.;
Towards a standard for embedded core test: an example
1999 / IEEE / 0-7803-5753-1
By: Taylor, T.; Kapur, R.; Zorian, Y.; Marinissen, E.J.; Whetsel, L.;
HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs
1999 / IEEE / 0-7803-5753-1
By: Prinetto, P.; Chiusano, S.; Cataldo, S.; Benso, A.; Zorian, Y.;
Minimizing the number of test configurations for different FPGA families
1999 / IEEE / 0-7695-0315-2
By: Figuras, J.; Portal, J.M.; Renovell, M.; Zorian, Y.;
Yield improvement and repair trade-off for large embedded memories
2000 / IEEE / 0-7695-0537-6
By: Zorian, Y.;
Effective low power BIST for datapaths
2000 / IEEE / 0-7695-0537-6
By: Paschalis, A.; Kranitis, N.; Gizopoulos, D.; Zorian, Y.; Psarakis, M.;
Low power/energy BIST scheme for datapaths
2000 / IEEE / 0-7695-0613-5
By: Zorian, Y.; Psarakis, M.; Paschalis, A.; Krantitis, N.; Gizopoulos, D.;
Emerging trends in VLSI test and diagnosis
2000 / IEEE / 0-7695-0534-1
By: Zorian, Y.;
System chip test: how will it impact your design?
2000 / IEEE / 1-58113-187-9
By: Marinissen, E.J.; Zorian, Y.;
Analyzing the test generation problem for an application-oriented test of FPGAs
2000 / IEEE / 0-7695-0701-8
By: Zorian, Y.; Figueras, J.; Faure, P.; Portal, J.M.; Renovell, M.;
Some experiments in test pattern generation for FPGA-implemented combinational circuits
2000 / IEEE / 0-7695-0843-X
By: Faure, P.; Portal, J.M.; Renovell, M.; Zorian, Y.; Figueras, J.;
Sequential fault modeling and test pattern generation for CMOS iterative logic arrays
2000 / IEEE
By: Psarakis, M.; Zorian, Y.; Paschalis, A.; Gizopoulos, D.;
TOF: a tool for test pattern generation optimization of an FPGA application oriented test
2000 / IEEE / 0-7695-0887-1
By: Portal, J.M.; Renovell, M.; Zorian, Y.; Figueras, J.; Faure, P.;
On using IEEE P1500 SECT for test plug-n-play
2000 / IEEE / 0-7803-6546-1
By: Marinissen, E.J.; Zorian, Y.; Kapur, R.;
Different experiments in test generation for XILINX FPGAs
2000 / IEEE / 0-7803-6546-1
By: Zorian, Y.; Renovell, M.;
HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs
2000 / IEEE / 0-7803-6546-1
By: Ricciato, F.; Prinetto, P.; Di Carlo, S.; Chiusano, S.; Benso, A.; Zorian, Y.; Spadari, M.;
Power-/energy-efficient BIST schemes for processor data paths
2000 / IEEE
By: Gizopoulos, D.; Kranitis, N.; Zorian, Y.; Psarakis, M.; Paschalis, A.;
Test of future system-on-chips
2000 / IEEE / 0-7803-6445-7
By: Rodgers, M.J.; Dey, S.; Zorian, Y.;
Deterministic software-based self-testing of embedded processor cores
2001 / IEEE / 0-7695-0993-2
By: Gizopoulos, D.; Paschalis, A.; Zorian, Y.; Psarakis, M.; Kranitis, N.;
An effective deterministic BIST scheme for shifter/accumulator pairs in datapaths
2001 / IEEE / 0-7695-1025-6
By: Kranitis, N.; Zorian, Y.; Paschalis, A.; Gizopoulos, D.; Psarakis, M.;
Robust and low-cost BIST architectures for sequential fault testing in datapath multipliers
2001 / IEEE / 0-7695-1122-8
By: Psarakis, M.; Paschalis, A.; Kranitis, N.; Zorian, Y.; Gizopoulos, D.;
An approach for evaluation of redundancy analysis algorithms
2001 / IEEE / 0-7695-1242-9
By: Shoukourian, S.; Zorian, Y.; Vardanian, V.;

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