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Author: Singh, A.D.

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Channel capacity of adaptive receivers with L-SC systems in Hoyt (Nakagami-q) fading channels
2011 / IEEE / 978-1-4577-1109-1
By: Subadar, R.; Singh, A.D.;
Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations
2011 / IEEE / 978-1-4577-1984-4
By: Chatterjee, A.; Singh, A.D.; Xi Qian;
Scan based two-pattern tests: should they target opens instead of TDFs?
2015 / IEEE
By: Singh, A.D.;
Ophthalmic Radiation Therapy
2013 / Karger Medical and Scientific Publishers / 9783318024401
By: Pelayes, D.E.; Seregard, S.; Singh, A.D.;
FNA Cytology of Ophthalmic Tumors
2012 / Karger Medical and Scientific Publishers / 9783805598705
By: Biscotti, C.V.; Singh, A.D.;
Interstitial redundancy: an area efficient fault tolerance scheme for large area VLSI processor arrays
1988 / IEEE
By: Singh, A.D.;
Near optimal embedding of binary tree architecture in VLSI
1988 / IEEE / 0-8186-0865-X
By: Singh, A.D.; Youn, H.Y.;
On implementing large binary tree architectures in VLSI and WSI
1989 / IEEE
By: Youn, H.Y.; Singh, A.D.;
Fault-tolerant systems
1990 / IEEE
By: Murugesan, S.; Singh, A.D.;
Fault tolerance in VLSI circuits
1990 / IEEE
By: Singh, A.D.; Koren, I.;
Defect tolerance scheme for gigaFLOP WSI architectures
1990 / IEEE / 0-8186-9013-5
By: Singh, A.D.; Hee yong Youn;
Yield modeling and optimization of large redundant RAMs
1990 / IEEE / 0-8186-9013-5
By: Ganapathy, K.N.; Pradhan, D.K.; Singh, A.D.;
An efficient channel routing algorithm for defective arrays
1989 / IEEE / 0-8186-1986-4
By: Youn, H.Y.; Singh, A.D.;
A modular fault-tolerant binary tree architecture with short links
1991 / IEEE
By: Singh, A.D.; Youn, H.Y.;
Yield optimization in large RAM's with hierarchical redundancy
1991 / IEEE
By: Ganapathy, K.N.; Pradhan, D.K.; Singh, A.D.;
Modelling correlated transient failures in fault-tolerant systems
1989 / IEEE / 0-8186-1959-7
By: Singh, A.D.; Krishna, C.M.;
Fault tolerant interconnect for on-wafer processor communication
1990 / IEEE
By: Singh, A.D.; Youn, H.Y.;
A new processor interconnection structure for fault tolerant processor arrays
1991 / IEEE / 0-8186-2125-7
By: Hee Yong Youn; Singh, A.D.;
Analysis of the die test optimization algorithm for negative binomial yield statistics
1992 / IEEE / 0-7803-0623-6
By: Krishna, C.M.; Singh, A.D.;
Chip test optimization using defect clustering information
1992 / IEEE / 0-8186-2875-8
By: Singh, A.D.; Krishna, C.M.;
Reliability of checkpointed real-time systems using time redundancy
1993 / IEEE
By: Krishna, C.M.; Singh, A.D.;
On optimizing VLSI testing for product quality using die-yield prediction
1993 / IEEE
By: Singh, A.D.; Krishna, C.M.;
Incorporating IDDQ testing in BIST: improved coverage through test diversity
1994 / IEEE / 0-8186-5440-6
By: Hurst, J.P.; Singh, A.D.;
The effect of defect clustering on test transparency and defect levels
1993 / IEEE / 0-8186-3830-3
By: Krishna, C.M.; Singh, A.D.;
Adaptive unanimous voting (UV) scheme for distributed self-diagnosis
1995 / IEEE
By: Singh, A.D.; Hee Yong Youn; Jae Young Lee;
Optimal configuration of redundant real-time systems in the face of correlated failure
1995 / IEEE
By: Krishna, C.M.; Singh, A.D.;
ADTS: an array defect-tolerance scheme for wafer scale gate arrays
1995 / IEEE / 0-8186-7107-6
By: Singh, A.D.;
On the effect of defect clustering on test transparency and IC test optimization
1996 / IEEE
By: Singh, A.D.; Krishna, C.M.;
A differential built-in current sensor design for high speed IDDQ testing
1995 / IEEE / 0-8186-6905-5
By: Hurst, J.P.; Singh, A.D.;
An experimental evaluation of the differential BICS for I/sub DDQ/ testing
1995 / IEEE / 0-8186-7000-2
By: Singh, A.D.; Weber, W.W.;
On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction
1991 / IEEE / 0-8186-9156-5
By: Krishna, C.M.; Singh, A.D.;
IDDQ testing of CMOS opens: an experimental study
1995 / IEEE / 0-7803-2992-9
By: Rasheed, H.; Singh, A.D.; Weber, W.W.;
A differential built-in current sensor design for high-speed IDDQ testing
1997 / IEEE
By: Hurst, J.P.; Singh, A.D.;
An IDDQ sensor for concurrent timing error detection
1997 / IEEE / 0-8186-8168-3
By: Knight, C.G.; Nelson, V.P.; Singh, A.D.;
A comprehensive wafer oriented test evaluation (WOTE) scheme for the IDDQ testing of deep sub-micron technologies
1997 / IEEE / 0-8186-8123-3
By: Singh, A.D.;
Screening for known good die (KGD) based on defect clustering: an experimental study
1997 / IEEE / 0-7803-4209-7
By: Singh, A.D.; Krishna, C.M.; Nigh, P.;
A multi-mode scannable memory element for high test application efficiency and delay testing
1998 / IEEE / 0-8186-8436-4
By: Goessel, M.; Singh, A.D.; Sogomonyan, E.S.;
An IDDQ sensor for concurrent timing error detection
1998 / IEEE
By: Singh, A.D.; Knight, C.G.; Nelson, V.P.;
On Wafer Burn-in Strategies for MCM Die
1994 / IEEE / 0-930815-39-4
By: Singh, A.D.;
Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study
1999 / IEEE / 0-7803-5753-1
By: Singh, A.D.; Lakin, D.R., II;
Testability evaluation of sequential designs incorporating the multi-mode scannable memory element
1999 / IEEE / 0-7803-5753-1
By: Seuring, M.; Gossel, M.; Sogomonyan, E.S.; Singh, A.D.;
Burn-in failures and local region yield: an integrated field-reliability model
2001 / IEEE / 0-7695-1122-8
By: Singh, A.D.; Barnett, T.S.; Nelson, V.P.;
Estimating burn-in fall-out for redundant memory
2001 / IEEE / 0-7803-7169-0
By: Barnett, T.S.; Nelson, V.P.; Singh, A.D.;
Yield-reliability modeling for fault tolerant integrated circuits
2001 / IEEE / 0-7695-1203-8
By: Barnett, T.S.; Nelson, V.P.; Singh, A.D.;
Yield-reliability modeling: experimental verification and application to burn-in reduction
2002 / IEEE / 0-7695-1570-3
By: Grady, M.; Singh, A.D.; Barnett, T.S.; Purdy, K.;
Redundancy implications for early-life reliability: experimental verification of an integrated yield-reliability model
2002 / IEEE / 0-7803-7542-4
By: Singh, A.D.; Purdy, K.; Grady, M.; Barnett, T.S.;
Reliability evaluation for integrated circuit with defective interconnect under electromigration
2003 / IEEE / 0-7695-1881-8
By: Xiangdong Xuan; Chatterjee, A.; Singh, A.D.;
ARET for system-level IC reliability simulation
2003 / IEEE / 0-7803-7649-8
By: Xiangdong Xuan; Singh, A.D.; Chatterjee, A.;
Extending integrated-circuit yield-models to estimate early-life reliability
2003 / IEEE
By: Nelson, V.P.; Singh, A.D.; Barnett, T.S.;
IC reliability simulator ARET and its application in design-for-reliability
2003 / IEEE / 0-7695-1951-2
By: Chatterjee, A.; Xiangdong Xuan; Chisa, M.T.; Kim, N.P.; Singh, A.D.;
Relating yield models to burn-in fall-out in time
2003 / IEEE / 0-7803-8106-8
By: Singh, A.D.; Barnett, T.S.;
Experiments in detecting delay faults using multiple higher frequency clocks and results from neighboring die
2003 / IEEE / 0-7803-8106-8
By: Singh, A.D.; Haihua Yan;
Should nanometer circuits be periodically tested in the field?
2003 / IEEE / 0-7803-8106-8
By: Singh, A.D.;
Local redesign for reliability of CMOS digital circuits under device degradation
2004 / IEEE / 0-7803-8315-X
By: Chatterjee, A.; Xiangdong Xuan; Singh, A.D.;
Sizing CMOS circuits for increased transient error tolerance
2004 / IEEE / 0-7695-2180-0
By: Singh, A.D.; Chatterjee, A.; Diril, A.U.; Dhillon, Y.S.;
Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits
2004 / IEEE / 0-7695-2119-3
By: Singh, A.D.; Chatterjee, A.; Xiangdong Xuan;
Low-power dual V/sub th/ pseudo dual V/sub dd/ domino circuits
2004 / IEEE / 1-58113-947-0
By: Chatterjee, A.; Diril, A.U.; Dhillon, Y.S.; Singh, A.D.;
Reduce yield loss in delay defect detection in slack interval
2004 / IEEE / 0-7695-2235-1
By: Singh, A.D.; Haihua Yan;
A delay test to differentiate resistive interconnect faults from weak transistor defects
2005 / IEEE / 0-7695-2264-5
By: Haihua Yan; Singh, A.D.;
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages
2005 / IEEE / 0-7695-2264-5
By: Abhijit Chatterjee; Dhillon, Y.S.; Diril, A.U.; Singh, A.D.;
Evaluating the effectiveness of detecting delay defects in the slack interval: a simulation study
2004 / IEEE / 0-7803-8580-2
By: Singh, A.D.; Haihua Yan;
On the effectiveness of detecting small delay defects in the slack interval
2004 / IEEE / 0-7803-8950-6
By: Singh, A.D.; Haihua Yan;
Low voltage test in place of fast clock in DDSI delay test
2005 / IEEE / 0-7695-2301-3
By: Singh, A.D.; Gefu Xu; Haihua Yan;
Design of adaptive nanometer digital systems for effective control of soft error tolerance
2005 / IEEE / 0-7695-2314-5
By: Singh, A.D.; Chatterjee, A.; Dhillon, Y.S.; Diril, A.U.;
Low-power domino circuits using NMOS pull-up on off-critical paths
2005 / IEEE / 0-7803-8736-8
By: Dhillon, Y.S.; Diril, A.U.; Singh, A.D.; Chatterjee, A.;
A dual-Vt layout approach for statistical leakage variability minimization in nanometer CMOS
2005 / IEEE / 0-7695-2451-6
By: Ashouei, M.; De, V.; Singh, A.D.; Chatterjec, A.;
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages
2005 / IEEE
By: Chatterjee, A.; Dhillon, Y.S.; Diril, A.U.; Singh, A.D.;
Delay Defect Characterization Using Low Voltage Test
2005 / IEEE / 0-7695-2481-8
By: Gefu Xu; Singh, A.D.; Haihua Yan;
Statistical estimation of correlated leakage power variation and its application to leakage-aware design
2006 / IEEE / 0-7695-2502-4
By: Singh, A.D.; Chatterjee, A.; Ashouei, M.; Mak, T.M.; De, V.;
A self-timed structural test methodology for timing anomalies due to defects and process variations
2005 / IEEE / 0-7803-9038-5
By: Singh, A.D.;
A random access scans architecture to reduce hardware overhead
2005 / IEEE / 0-7803-9038-5
By: Agrawal, V.D.; Mudlapur, A.S.; Singh, A.D.;
Combining negative binomial and Weibull distributions for yield and reliability prediction
2006 / IEEE
By: Barnett, T.S.; Singh, A.D.; Purdy, K.G.; Grady, M.;
Output hazard-free transition tests for silicon calibrated scan based delay testing
2006 / IEEE / 0-7695-2514-8
By: Gefu Xu; Singh, A.D.;
Low Cost Launch-on-Shift Delay Test with Slow Scan Enable
2006 / IEEE / 0-7695-2566-0
By: Singh, A.D.; Gefu Xu;
Analysis and optimization of nanometer CMOS circuits for soft-error tolerance
2006 / IEEE
By: Singh, A.D.; Chatterjee, A.; Diril, A.U.; Dhillon, Y.S.;
Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules
1981 / IEEE
By: Singh, A.D.; Armstrong, J.R.; Gray, F.G.;
A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI)
2006 / IEEE
By: Haihua Yan; Singh, A.D.;
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations
2007 / IEEE / 0-7695-2762-0
By: Chatterjee, A.; Nisar, M.M.; Ashouei, M.; Diril, A.U.; Singh, A.D.;
Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing
2007 / IEEE / 0-7695-2762-0
By: Singh, A.D.; Gefu Xu;
Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan
2007 / IEEE / 0-7695-2890-2
By: Singh, A.D.; Gefu Xu;
Achieving high transition delay fault coverage with partial DTSFF scan chains
2007 / IEEE / 978-1-4244-1127-6
By: Singh, A.D.; Gefu Xu;
Scan Delay Testing of Nanometer SoCs
2008 / IEEE / 0-7695-3083-4
By: Singh, A.D.;
Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS
2008 / IEEE / 0-7695-3083-4
By: Ashouei, M.; Chatterjee, A.; Singh, A.D.;
Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects
2008 / IEEE / 978-1-4244-2402-3
By: Singh, A.D.;
Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic
2010 / IEEE
By: Ashouei, M.; Singh, A.D.; Chatterjee, A.;
Output Hazard-Free Transition Delay Fault Test Generation
2009 / IEEE / 978-0-7695-3598-2
By: Menon, S.; Agrawal, V.; Singh, A.D.;
A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS
2009 / IEEE / 978-0-7695-3839-6
By: Singh, A.D.;
On Minimization of Test Application Time for RAS
2010 / IEEE / 978-1-4244-5542-3
By: Saluja, K.K.; Singh, V.; Arpit, G.; Adiga, R.; Singh, A.D.; Fujiwara, H.;
Modified T-Flip-Flop based scan cell for RAS
2010 / IEEE / 978-1-4244-5835-6
By: Arpit, G.; Adiga, R.; Singh, A.D.; Saluja, K.K.; Singh, V.;
Modified Scan Flip-Flop for Low Power Testing
2010 / IEEE / 978-1-4244-8841-4
By: Satdev; Sinha, N.; Mishra, A.; Singh, A.D.; Chakravarty, S.; Singh, V.;
Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations
2011 / IEEE / 978-1-61284-327-8
By: Singh, A.D.; Faraz, A.; Mishra, K.; Chatterjee, A.;

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