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Author: Sha, E.H.-M.

Results

Minimizing Access Cost for Multiple Types of Memory Units in Embedded Systems Through Data Allocation and Scheduling
2012 / IEEE
By: Wei-Che Tseng; Jingtong Hu; Yibo Guo; Qingfeng Zhuge; Sha, E.H.-M.; Xue, S.J.;
A Novel Energy-Aware Fault Tolerance Mechanism for Wireless Sensor Networks
2011 / IEEE / 978-1-4577-1006-3
By: Sha, E.H.-M.; Zhong Ming; Zongming Fei; Jiayin Li; Jianning Liu; Meikang Qiu;
Optimal Data Allocation for Scratch-Pad Memory on Embedded Multi-core Systems
2011 / IEEE / 978-1-4577-1336-1
By: Yibo Guo; Sha, E.H.-M.; Meikang Qiu; Jingtong Hu; Qingfeng Zhuge;
Optimal Data Placement for Memory Architectures with Scratch-Pad Memories
2011 / IEEE / 978-1-4577-2135-9
By: Qingfeng Zhuge; Yibo Guo; Sha, E.H.-M.; Jingtong Hu;
Reconfigurability and reliability of systolic/wavefront arrays
1991 / IEEE / 0-7803-0003-3
By: Sha, E.H.-M.; Steiglitz, K.;
Design for easily applying test vectors to improve delay fault coverage
1991 / IEEE / 0-8186-2157-5
By: Sha, E.H.-M.; Chao, L.-F.;
Efficient distributed reconfiguration for binary trees on Diogenes model
1992 / IEEE / 0-7803-0605-8
By: Chao, L.-F.; Sha, E.H.-M.;
Explicit construction for reliable reconfigurable array architectures
1991 / IEEE / 0-8186-2310-1
By: Sha, E.H.-M.; Steiglitz, K.;
Rate-optimal static scheduling for DSP data-flow programs
1993 / IEEE / 0-8186-3430-8
By: Sha, E.H.-M.; Chao, L.-F.;
Run-time error detection in arrays based on the data-dependency graph
1992 / IEEE / 0-7803-0532-9
By: Steiglitz, K.; Sha, E.H.-M.;
Unfolding and retiming data-flow DSP programs for RISC multiprocessor scheduling
1992 / IEEE / 0-7803-0532-9
By: Chao, L.-F.; Sha, E.H.-M.;
Algorithms for min-cut linear arrangements of outerplanar graphs
1992 / IEEE / 0-7803-0593-0
By: Chao, L.-F.; Sha, E.H.-M.;
Reconfigurability and reliability of systolic/wavefront arrays
1993 / IEEE
By: Sha, E.H.-M.; Steiglitz, K.;
Maintaining bipartite matchings in the presence of failures
1993 / IEEE / 0-8186-3442-1
By: Steiglitz, K.; Sha, E.H.-M.;
Static scheduling of uniform nested loops
1993 / IEEE / 0-8186-3442-1
By: Sha, E.H.-M.; Chao, L.-F.;
Global node reduction of linear systems using ratio analysis
1994 / IEEE / 0-8186-5785-5
By: Sha, E.H.-M.; Sheliga, M.;
Efficient retiming and unfolding
1993 / IEEE / 0-7803-0946-4
By: Sha, E.H.-M.; Chao, L.-F.;
Communication sensitive rotation scheduling
1994 / IEEE / 0-8186-6565-3
By: Tongsima, S.; Sha, E.H.-M.; Passos, N.L.;
Optimizing synchronous systems for multi-dimensional applications
1995 / IEEE / 0-8186-7039-8
By: Liang-Fang Chao; Sha, E.H.-M.; Passos, N.L.;
Memory/time optimization of 2-D filters
1995 / IEEE / 0-7803-2431-5
By: Passos, N.L.; Sha, E.H.-M.;
Rate-optimal scheduling for cyclo-static and periodic schedules
1995 / IEEE / 0-7803-2431-5
By: Liang-Fang Chao; Sha, E.H.-M.;
Optimizing DSP flow graphs via schedule-based multidimensional retiming
1996 / IEEE
By: Bass, S.C.; Sha, E.H.-M.; Passos, N.L.;
A parameterized index-generator for the multi-dimensional interleaving optimization
1996 / IEEE / 0-8186-7502-0
By: Sha, E.H.-M.; Passos, N.L.;
Rapid prototyping for fuzzy systems
1996 / IEEE / 0-8186-7502-0
By: Sha, E.H.-M.; Tongsima, S.; Chantrapornchai, C.;
Synchronous circuit optimization via multidimensional retiming
1996 / IEEE
By: Sha, E.H.-M.; Passos, N.L.;
Multi-dimensional interleaving for time-and-memory design optimization
1995 / IEEE / 0-8186-7165-3
By: Liang-Fang Chao; Sha, E.H.-M.; Passes, N.L.;
Polynomial-time nested loop fusion with full parallelism
1996 / IEEE / 0-8186-7623-X
By: Sha, E.H.-M.; Passos, N.L.; Chenhua Lang;
Minimization of fuzzy systems based on fuzzy inference graphs
1996 / IEEE / 0-7803-3073-0
By: Sha, E.H.-M.; Tongsima, S.; Chantrapornchai, C.;
Static communication scheduling for minimizing collisions in application specific parallel systems
1996 / IEEE / 0-8186-7542-X
By: Sha, E.H.-M.; Surma, D.R.;
Hardware/software co-design for DSP applications via the HMS framework
1996 / IEEE / 0-7803-3192-3
By: Sha, E.H.-M.; Sheliga, M.;
Achieving full parallelism using multidimensional retiming
1996 / IEEE
By: Passos, N.L.; Sha, E.H.-M.;
Optimal communication scheduling based on collision graph model
1996 / IEEE / 0-7803-3192-3
By: Surma, D.R.; Sha, E.H.-M.; Tongsima, S.;
Synthesis of multi-dimensional applications in VHDL
1996 / IEEE / 0-8186-7554-3
By: Passos, N.L.; Sha, E.H.-M.;
Communication-sensitive loop scheduling for DSP applications
1997 / IEEE
By: Passos, N.L.; Sha, E.H.-M.; Tongsima, S.;
Scheduling with confidence for probabilistic data-flow graphs
1997 / IEEE / 0-8186-7904-2
By: Sha, E.H.-M.; Chantrapornchai, C.; Tongsima, S.; Passos, N.L.;
Algorithm and hardware support for branch anticipation
1997 / IEEE / 0-8186-7904-2
By: Yu, T.Z.; Ju, R.D.-C.; Passos, N.; Sha, E.H.-M.;
Rotation scheduling: a loop pipelining algorithm
1997 / IEEE
By: LaPaugh, A.S.; Liang-Fang Chao; Sha, E.H.-M.;
Imprecise task schedule optimization
1997 / IEEE / 0-7803-3796-4
By: Chantrapornchai, C.; Sha, E.H.-M.; Tongsima, S.;
Probabilistic rotation: scheduling graphs with uncertain execution time
1997 / IEEE / 0-8186-8108-X
By: Sha, E.H.-M.; Chantrapornchai, C.; Tongsima, S.; Passos, N.;
Rapid system design framework for fuzzy applications
1997 / IEEE / 0-7803-3694-1
By: Tongsima, S.; Sheliga, M.; Chantrapornchai, C.; Sha, E.H.-M.;
Optimizing data scheduling on processor-in-memory arrays
1998 / IEEE / 0-8186-8404-6
By: Sha, E.H.-M.; Tian, Y.; Kogge, P.M.; Chantrapornchai, C.;
Loop scheduling algorithms for power reduction
1998 / IEEE / 0-7803-4428-6
By: Yu, T.Z.; Sha, E.H.-M.; Fei Chen;
Graph transformation for communication minimization using retiming
1998 / IEEE / 0-7803-4455-3
By: Sheliga, M.; Sha, E.H.-M.; Fei Chen; Zhihong Yu;
Optimizing circuits with confidence probability using probabilistic retiming
1998 / IEEE / 0-7803-4455-3
By: Tongsima, S.; Passos, N.L.; Sha, E.H.-M.; Chantrapornchai, C.;
Compile-time priority assignment and re-routing for communication minimization in parallel systems
1998 / IEEE / 0-7803-4455-3
By: Surma, D.R.; Kogge, P.M.; Sha, E.H.-M.;
Loop scheduling algorithm for timing and memory operation minimization with register constraint
1998 / IEEE / 0-7803-4997-0
By: Chen, F.; Sha, E.H.-M.; Tongsima, S.;
Loop Scheduling Algorithm For Timing And Memory Operation Minimization With Register Constraint
1998 / IEEE / 0-7803-4997-0
By: Chen, F.; Sha, E.H.-M.; Tongsima, S.;
Efficient algorithms for finding highly acceptable designs based on module-utility selections
1999 / IEEE / 0-7695-0104-4
By: Chantrapornchai, C.; Xiaobo Hu; Sha, E.H.-M.;
Unfolding probabilistic data-flow graphs under different timing models
1999 / IEEE / 0-7803-5041-3
By: Tongsima, S.; Sha, E.H.-M.; O'Neil, T.W.;
Extended retiming: optimal scheduling via a graph-theoretical approach
1999 / IEEE / 0-7803-5041-3
By: O'Neil, T.W.; Tongsima, S.; Sha, E.H.-M.;
Efficient scheduling for imprecise timing based on fuzzy theory
1998 / IEEE / 0-8186-8914-5
By: Chantrapornchai, C.; Hu, X.S.; Sha, E.H.-M.;
Nested loops optimization for multiprocessor architecture design
1998 / IEEE / 0-8186-8914-5
By: Passos, N.L.; Leonardi, A.; Sha, E.H.-M.;
A probabilistic performance metric for real-time system design
1999 / IEEE / 1-58113-132-1
By: Sha, E.H.-M.; Hu, X.; Zhou, T.;
Probabilistic loop scheduling for applications with uncertain execution time
2000 / IEEE
By: Tongsima, S.; Passos, N.L.; Surma, D.R.; Chantrapornchai, C.; Sha, E.H.-M.;
Efficient design exploration based on module utility selection
2000 / IEEE
By: Chantrapornchai, C.; Hu, X.S.; Sha, E.H.-M.;
Application specific image compression for virtual conferencing
2000 / IEEE / 0-7695-0540-6
By: Sha, E.H.-M.; Furgeson, J.C.; Jiangfeng Ding;
Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications
2000 / IEEE / 1-58113-187-9
By: Sha, E.H.-M.; Kirkpatrick, M.; Wang, Z.;
Optimizing overall loop schedules using prefetching and partitioning
2000 / IEEE
By: Sha, E.H.-M.; O'Neil, T.W.; Fei Chen;
Communication reduction in multiple multicasts based on hybrid static-dynamic scheduling
2000 / IEEE
By: Surma, D.R.; Sha, E.H.-M.;
QoS measures and implementations based on various models for real-time communications
2000 / IEEE / 0-7695-0559-7
By: Kirkpatrick, M.; Ding, J.; Sha, E.H.-M.;
Implementing parallelism and scheduling data flow graphs on Java virtual machine
2001 / IEEE / 0-7803-7041-4
By: Sha, E.H.-M.; Xu, J.;
Retiming synchronous data-flow graphs to reduce execution time
2001 / IEEE
By: Sha, E.H.-M.; O'Neil, T.W.;
Scheduling and partitioning for multiple loop nests
2001 / IEEE / 1-58113-418-5
By: Zhong Wang; Sha, E.H.-M.; Qingfeng Zhuge;
Optimal loop scheduling for hiding memory latency based on two-level partitioning and prefetching
2001 / IEEE
By: Zhong Wang; Sha, E.H.-M.; O'Neil, T.W.;
Minimum dynamic update for shortest path tree construction
2001 / IEEE / 0-7803-7206-9
By: Bin Xiao; Sha, E.H.-M.; Qingfeng ZhuGe;
Estimating probabilistic timing performance for real-time embedded systems
2001 / IEEE
By: Hu, X.S.; Sha, E.H.-M.; Tao Zhou;
Variable partitioning and scheduling of multiple memory architectures for DSP
2002 / IEEE / 0-7695-1573-8
By: Sha, E.H.-M.; Xiao, B.; Zhuge, Q.;
Optimal code size reduction for software-pipelined loops on DSP applications
2002 / IEEE / 0-7695-1677-7
By: Zili Shao; Qingfeng Zhuge; Sha, E.H.-M.;
Register aware scheduling for distributed cache clustered architecture
2003 / IEEE / 0-7803-7659-5
By: Sha, E.H.-M.; Xiaobo Sharon Hu; Zhong Wang;
Optimal code size reduction for software-pipelined and unfolded loops
2002 / IEEE / 1-58113-576-9
By: Chantana Chantrapornchai; Sha, E.H.-M.; Zili Shao; Bin Xiao; Qingfeng Zhuge;
Defending embedded systems against buffer overflow via hardware/software
2003 / IEEE / 0-7695-2041-3
By: Zhuge, Q.; Shao, Z.; Sha, E.H.-M.; He, Y.;
Efficient variable partitioning and scheduling for DSP processors with multiple memory modules
2004 / IEEE
By: Chantrapornchai, C.; Bin Xiao; Sha, E.H.-M.; Qingfeng Zhuge;
Security protection and checking in embedded system integration against buffer overflow attacks
2004 / IEEE / 0-7695-2108-8
By: Qingfeng Zhuge; Chun Xue; Zili Shao; Bin Xiao; Sha, E.H.-M.;
Approximation algorithms design for disk partial covering problem
2004 / IEEE / 0-7695-2135-5
By: Sha, E.H.-M.; Yi He; Qingfeng Zhuge; Jiannong Cao; Bin Xiao;
Assignment and scheduling of real-time DSP applications for heterogeneous functional units
2004 / IEEE / 0-7695-2132-0
By: Zhuge, Q.; Shao, Z.; Sha, E.H.-M.; Liu, M.; Xue, C.; He, Y.;
Timing optimization of nested loops considering code size for DSP applications
2004 / IEEE / 0-7695-2197-5
By: Qingfeng Zhuge; Sha, E.H.-M.; Zili Shao;
Switching-activity minimization on instruction-level loop for VLIW DSP applications
2004 / IEEE / 0-7695-2226-2
By: Qingfeng Zhuge; Zili Shao; Sha, E.H.-M.; Bin Xiao; Meilin Liu;
Dynamic shortest path tree update for multiple link state decrements
2004 / IEEE / 0-7803-8794-5
By: Bin Xiao; Sha, E.H.-M.; Zili Shao; Qingfeng Zhuge; Jiannong Cao;
Register-constrained inclusion scheduling for imprecise specification
2004 / IEEE / 0-7803-8560-8
By: Sha, E.H.-M.; Surakumpolthorn, W.; Chantrapornchai, C.;
Efficient assignment and scheduling for heterogeneous DSP systems
2005 / IEEE
By: Zhuge, Q.; Shao, Z.; Sha, E.H.-M.; Xue, C.;
High-level synthesis for DSP applications using heterogeneous functional units
2005 / IEEE / 0-7803-8736-8
By: Qingfeng Zhuge; Zili Shao; Sha, E.H.-M.; Bin Xiao; Chun Xue;
Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems
2005 / IEEE / 0-7695-2281-5
By: Shao, Z.; Ying Chen; Sha, E.H.-M.; Bin Xiao; Xue, C.; Zhuge, Q.;
Universal routing in distributed networks
2005 / IEEE / 0-7695-2281-5
By: Sha, E.H.-M.; Chen, K.F.; Bin Xiao;
An active detecting method against SYN flooding attack
2005 / IEEE / 0-7695-2281-5
By: Yanxiang He; Wei Chen; Bin Xiao; Sha, E.H.-M.;
Maximum loop distribution and fusion for two-level loops considering code size
2005 / IEEE / 0-7695-2509-1
By: Xue, C.; Shao, Z.; Zhuge, Q.; Liu, M.; Sha, E.H.-M.; Qiu, M.;
A fast noniterative scheduler for input-queued switches with unbuffered crossbars
2005 / IEEE / 0-7695-2509-1
By: Zheng, S.Q.; Sha, E.H.-M.; Chen, K.F.;
Security protection and checking for embedded system integration against buffer overflow attacks via hardware/software
2006 / IEEE
By: Qiu, M.; Zhuge, Q.; Xue, C.; Zili Shao; Sha, E.H.-M.; Bin Xiao;
Loop scheduling with complete memory latency hiding on multi-core architecture
2006 / IEEE / 0-7695-2612-8
By: Chun Xue; Sha, E.H.-M.; Meikane Qiu; Meilin Liu; Zili Shao;
Optimizing Address Assignment and Scheduling for DSPs With Multiple Functional Units
2006 / IEEE
By: Bin Xiao; Qingfeng Zhuge; Zili Shao; Chun Xue; Sha, E.H.-M.; Meilin Liu;
Design Exploration With Imprecise Latency and Register Constraints
2006 / IEEE
By: Chantrapornchai, C.; Sha, E.H.-M.; Surakampontorn, W.;
Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability
2006 / IEEE / 0-7695-2682-9
By: Qingfeng Zhuge; Chun Xue; Meikang Qiu; Sha, E.H.-M.; Liu, M.; Zili Shao;
Iterational retiming: maximize iteration-level parallelism for nested loops
2005 / IEEE / 1-59593-161-9
By: Zili Shao; Chun Xue; Liu, M.; Sha, E.H.-M.;
Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems
2007 / IEEE
By: Chun Xue; Ying Chen; Meng Wang; Zili Shao; Sha, E.H.-M.; Yang, L.T.; Meikang Qiu;
Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors
2007 / IEEE / 0-7695-2975-5
By: Chun Jason Xue; Zili Shao; Meng Wang; Sha, E.H.-M.;
Optimized Address Assignment With Array and Loop Transformations for Minimizing Schedule Length
2008 / IEEE
By: Sha, E.H.-M.; Meng Wang; Zili Shao; Zhiping Jia; Chun Jason Xue;
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints
2008 / IEEE / 978-3-9810801-3-1
By: Xue, C.J.; Meikang Qiu; Sha, E.H.-M.;
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
2008 / IEEE / 978-1-4244-1483-3
By: Zili Shao; Tiantian Liu; Chun Jason Xue; Sha, E.H.-M.; Weijia Jia; Zhiping Jia; Jingtong Hu;
Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory
2008 / IEEE / 978-1-4244-1960-9
By: Meikang Qiu; Sha, E.H.-M.; Wei-Che Tseng; Jingtong Aaron Hu; Chun Jason Xue; Jiande Wu;
Failure Rate Minimization with Multiple Function Unit Scheduling for Heterogeneous WSNs
2008 / IEEE / 978-1-4244-2324-8
By: Jing Deng; Meikang Qiu; Sha, E.H.-M.;
Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment
2008 / IEEE / 978-0-7695-3492-3
By: Sha, E.H.-M.; Yi He; Jingtong Hu; Jiande Wu; Meikang Qiu;

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