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Author: Rothschild, A.

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Laser ablation of AlOx and AlOx/SiNx backside passivation layers for advanced cell architectures
2011 / IEEE / 978-1-4244-9965-6
By: Jaffrennou, P.; Rothschild, A.; Szlufcik, J.; Lombardet, B.; Moors, M.; Penaud, J.; Duerinckx, F.; Das, J.; Uruena, A.;
Spatially-separated atomic layer deposition of Al2O3, a new option for high-throughput si solar cell passivation
2011 / IEEE / 978-1-4244-9965-6
By: Lorenz, A.; Roozeboom, F.; Stals, W.; Werner, F.; Vermang, B.; Schmidt, J.; Rothschild, A.; Poodt, P.; Gortzen, R.; Mertens, R.; Poortmans, J.; John, J.;
Impact of ageing on AlOx layer passivation properties for advanced cell architectures
2011 / IEEE / 978-1-4244-9965-6
By: Lombardet, B.; Ngamo, M.; Naber, R.; Jaffrennou, P.; Rothschild, A.; Penaud, J.;
In-line electrical characterization of ultrathin gate dielectric films
2002 / IEEE / 0-7803-7158-5
By: Pique, D.; Date, L.; Xiafang Zhang; Eason, K.; Conard, T.; Cubaynes, F.; Schaekers, M.; Passefort, S.; Rothschild, A.;
Ultra-thin oxynitride gate dielectrics by pulsed-RF DPN for 65 nm general purpose CMOS applications
2003 / IEEE / 0-7803-7999-3
By: Cubaynes, F.N.; Veloso, A.; Jurczak, M.; Dachs, C.; Schaekers, M.; Date, L.; Olsen, C.; O'Connor, R.; Degraeve, R.; Mertens, S.; Rothschild, A.;
RPN Oxynitride Gate Dielectrics for 90 nm Low Power CMOS Applications
2002 / IEEE / 88-900847-8-2
By: Dachs, C.; Murto, R.; Al-Shareef, A.; Schaekers, M.; Rothschild, A.; Mertens, S.; Rooyackers, R.; Cubaynes, F.; Jurczak, M.; Veloso, A.; Badenes, G.;
Gate Dielectrics for High Performance and Low Power CMOS SoC Applications
2002 / IEEE / 88-900847-8-2
By: Cubaynes, F.; Dachs, C.; Murto, R.; Al-Shareef, H.; Pique, D.; Date, L.; Badenes, G.; Schaekers, M.; Da Rold, M.; Petry, J.; Conard, T.; Rothschild, A.; Degraeve, R.; Detcheverry, C.; Zegers, A.; Venezia, V.; Schmitz, J.; Stolk, P.; Jurczak, M.; Henson, K.;
NO oxides for low noise 0.18um analog CMOS
2001 / IEEE / 2-914601-01-8
By: Simoen, E.; De Jaeger, B.; Lietaer, N.; Rothschild, A.; De Keersgieter, A.; Decoutere, S.; Da Rold, M.;
Low Power CMOS Featuring Dual Work Function FUSI on HfSiON and 17ps Inverter Delay
2006 / IEEE / 1-4244-0005-8
By: Vrancken, C.; Absil, P.P.M.; Nackaerts, A.; Ramos, J.; Froment, B.; Rothschild, A.; Niwa, M.; Satoru, I.; Brus, S.; Mitsuhashi, R.; Kerner, C.; Chiarella, T.; Tigelaar, H.; Van Dal, M.; Yu, H.; Lauwers, A.; Veloso, A.; Hoffmann, T.; Biesemans, S.; Kittl, J.A.; Jurczak, M.;
Polycrystalline Si optimization for 45nm node Ni-FUSI gate
2006 / IEEE / 1-4244-0161-5
By: Schaekers, M.; Shi, X.; Date, L.; Rosseel, E.; Brus, S.; Richard, O.; Moussa, A.; Everaert, J.L.; Rothschild, A.;
Ni-based FUSI gates: CMOS Integration for 45nm node and beyond
2006 / IEEE / 1-4244-0438-X
By: Kerner, C.; Kauerauf, T.; Van Dal, M.; Chiarella, T.; Tigelaar, H.; Yu, H.; Lauwers, A.; Veloso, A.; Hoffmann, T.; Kittl, J.A.; Biesemans, S.; Jurczak, M.; Absil, P.P.; Vrancken, C.; Brus, S.; Rosmeulen, M.; Nackaerts, A.; Ramos, J.; Froment, B.; Rothschild, A.; Niwa, M.; Satoru, I.; Mitsuhashi, R.; Shickova, A.;
FUSI Specific Yield Monitoring Enabling Improved Circuit Performance and Fast Feedback to Production
2007 / IEEE / 1-4244-0780-X
By: Jurczak, M.; Rothschild, A.; Lauwers, A.; Ramos, J.; Veloso, A.; Nackaerts, A.; Kerner, C.; Tigelaar, H.; Rosmeulen, M.; Chiarella, T.; Hoffmann, T.; Biesemans, S.; Absil, P.; Debusschere, I.; de Potter, M.; Verbeeck, R.; Kittl, J.A.; Yu, H.; Witters, L.;
Achieving 9ps unloaded ring oscillator delay in FuSI/HfSiON with 0.8 nm EOT
2007 / IEEE / 978-4-900784-03-1
By: Niwa, M.; Lauwers, A.; Yoshinao, H.; Shickova, A.; Vrancken, C.; Mitsuhashi, R.; Hoffmann, T.; Chiarella, T.; Kerner, C.; Everaert, J.L.; Shi, X.; Rothschild, A.; Biesemans, S.; Absil, P.; Kittl, J.; Veloso, A.;
Addressing Key Concerns for Implementation of Ni FUSI into Manufacturing for 45/32 nm CMOS
2007 / IEEE / 978-4-900784-03-1
By: Shickova, A.; Kittl, J.A.; Rothschild, A.; Aoulaiche, M.; Sahhaf, S.A.; Kaczer, B.; Veloso, A.; Torregiani, C.; Pantisano, L.; Lauwers, A.; Zahid, M.; Rost, T.; Tigelaar, H.; Pas, M.; Fretwell, J.; McCormack, J.; Hoffmann, T.; Kemer, C.; Chiarella, T.; Bras, S.; Harada, Y.; Niwa, M.; Kaushik, V.; Maes, H.; Absil, P.P.; Groeseneken, G.; Biesemans, S.; Kauerauf, T.;
Cost-Effective Low $V_{t}$ Ni-FUSI CMOS on SiON by Means of Al Implant (pMOS) and $\hbox{Yb}{+}\hbox{P}$ Coimplant (nMOS)
2008 / IEEE
By: Demeurisse, C.; Mertens, S.; Pawlak, M.A.; Whittemore, G.; Ameen, M.; Mitsuhashi, R.; Satoru, I.; Vrancken, C.; Niwa, M.; Rothschild, A.; Demand, M.; Kerner, C.; Hoffmann, T.; Yu, H.Y.; Chang, S.-Z.; Veloso, A.; Lauwers, A.; Kittl, J.A.; Biesemans, S.; Absil, P.; Vandervorst, W.;
Improvement of TANOS NAND Flash Performance by the Optimization of a Sealing Layer
2008 / IEEE / 978-1-4244-1547-2
By: Rothschild, A.; Furnemont, A.; Breuil, L.; Van Houdt, J.; Cacciato, A.; Van den bosch, G.;
Nitride Engineering for Improved Erase Performance and Retention of TANOS NAND Flash Memory
2008 / IEEE / 978-1-4244-1547-2
By: Van Houdt, J.; Ganguly, U.; Olsen, C.; Rothschild, A.; Cacciato, A.; Van den bosch, G.; Breuil, L.; Degraeve, R.; Zahid, M.B.; Furnemont, A.;
Electrospun nanostructured TiO2 gas sensors
2008 / IEEE / 978-1-4244-2580-8
By: Rothschild, A.; Landau, O.; Zussman, E.;
Investigation of Window Instability in Program/Erase Cycling of TANOS NAND Flash Memory
2009 / IEEE / 978-1-4244-3762-7
By: Jurczak, M.; Rothschild, A.; Cacciato, A.; Breuil, L.; Van den Bosch, G.; Van Houdt, J.;
Experimental evaluation of trapping efficiency in silicon nitride based charge trapping memories
2009 / IEEE / 978-1-4244-4351-2
By: Breuil, L.; Van den bosch, G.; Arreghini, A.; Suhane, A.; Cacciato, A.; Van Houdt, J.; De Meyer, K.; Jurczak, M.; Rothschild, A.;
O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory
2009 / IEEE / 978-1-4244-4351-2
By: Van Houdt, J.; Kittl, J.A.; Debusschere, I.; Cacciato, A.; Jurczak, M.; Franquet, A.; Conard, T.; Richard, O.; Van den bosch, G.; Breuil, L.; Rothschild, A.; Schreutelkamp, R.; Boelen, P.; Date, L.; Ganguly, U.;
Impact of Top-Surface Tunnel-Oxide Nitridation on Flash Memory Performance and Reliability
2010 / IEEE
By: Ganguly, U.; Swenberg, J.; Rothschild, A.; Cho, Y.; Date, L.; Wellekens, D.; Guarini, T.;
Recovery of the MOSFET and Circuit Functionality After the Dielectric Breakdown of Ultrathin High-$k$ Gate Stacks
2010 / IEEE
By: Crespo-Yepes, A.; Martin-Martinez, J.; Rothschild, A.; Rodriguez, R.; Nafria, M.; Aymerich, X.;
Investigation of rare-earth aluminates as alternative trapping materials in Flash memories
2010 / IEEE / 978-1-4244-6661-0
By: Cacciato, A.; Van Houdt, J.; Kittl, J.A.; Debusschere, I.; Jurczak, M.; Bender, H.; Breuil, L.; Van Den Bosch, G.; Rothschild, A.; Swerts, J.; Adelmann, C.; Arreghini, A.; Richard, O.; Suhane, A.;
Injected Charge to Recovery as a Parameter to Characterize the Breakdown Reversibility of Ultrathin HfSiON Gate Dielectric
2011 / IEEE
By: Rothschild, A.; Martin-Martinez, J.; Crespo-Yepes, A.; Aymerich, X.; Nafria, M.; Rodriguez, R.;

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