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Author: Richard, O.

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A 65-nm CMOS Fully Integrated Transceiver Module for 60-GHz Wireless HD Applications

2011 / IEEE
By: Vincent, P.; Siligaris, A.; Cathelin, A.; Busson, P.; Pilard, R.; Yamamoto, S.D.; Dussopt, L.; Lanteri, J.; Dehos, C.; Ferragut, R.; Chaix, F.; Mounet, C.; Martineau, B.; Richard, O.; Belot, D.;

Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory

2011 / IEEE
By: Van Houdt, J.; Van den bosch, G.; Van Aerde, S.; Richard, O.; Douhard, B.; Vrancken, C.; Debusschere, I.; Paraschiv, V.; De Keersgieter, A.; Breuil, L.; Cacciato, A.; Arreghini, A.; Blomme, P.; Kar, G.S.;

Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology

2012 / IEEE
By: Breuil, L.; Wellekens, D.; Cacciato, A.; Blomme, P.; Van Houdt, J.; Rosmeulen, M.; Richard, O.; Debusschere, I.; Vrancken, C.; Locorotondo, S.; Kar, G.S.;

Evidences of anodic-oxidation reset mechanism in TiN\NiO\Ni RRAM cells

2011 / IEEE / 978-1-4244-9949-6
By: Chou, H.; Wouters, D.J.; Govoreanu, B.; Degraeve, R.; Goux, L.; Altimime, L.; Jurczak, M.; Afanas'ev, V.V.; Kittl, J.A.; Richard, O.; Kubicek, S.; Wang, X.P.; Toeller, M.; Meersschaut, J.;

Large scale P2P discovery middleware demonstration

2011 / IEEE / 978-1-4577-0149-8
By: Haiwu He; Chuffart, F.; Caron, E.; Richard, O.; Le Brouster, P.; Lamani, A.;

Understanding of Trap-Assisted Tunneling Current - Assisted by Oxygen Vacancies in RuOx/SrTiO3/TiN MIM Capacitor for the DRAM Application

2012 / IEEE / 978-1-4673-1081-9
By: Starschich, S.; Kaczer, B.; Kim, M.-S.; Kittl, J.A.; Altimime, L.; Debusschere, I.; Popovici, M.; Van Elshocht, S.; Vrancken, C.; Tomida, K.; Richard, O.; Swerts, J.;

Process-improved RRAM cell performance and reliability and paving the way for manufacturability and scalability for high density memory application

2012 / IEEE / 978-1-4673-0847-2
By: Paraschiv, V.; Wouters, D.J.; Chen, Y.-Y.; Fantini, A.; Kar, G.S.; Jurczak, M.; Altimime, L.; Govoreanu, B.; Vandeweyer, T.; Richard, O.; Brus, S.; Tielens, H.; Jossart, N.; Hody, H.;

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

2014 / IEEE
By: Waldron, N.; Merckling, C.; Thean, A.V-Y.; Collaert, N.; Barla, K.; Vandervorst, W.; Heyns, M.; Caymax, M.; Boccardi, G.; Bender, H.; Guo, W.; Ong, P.; Teugels, L.; Ansar, S.; Tsvetanova, D.; Sebaai, F.; van Dorp, D.H.; Milenin, A.; Lin, D.; Nyns, L.; Mitard, J.; Pourghaderi, A.; Douhard, B.; Richard, O.;

Integration of a multi-layer Inter-Gate Dielectric with hybrid floating gate towards 10nm planar NAND flash

2014 / IEEE
By: Lisoni, J. G.; Tan, C.-L.; Blomme, P.; Breuil, L.; Souriau, L.; Van den bosch, G.; Bender, H.; Richard, O.; Zahid, M. B.; Van Houdt, J.;

Performance characteristics of a network of commodity multiprocessors for the NAS benchmarks using a hybrid memory model

1999 / IEEE / 0-7695-0425-6
By: Richard, O.; Cappello, F.;

Investigating the performance of two programming models for clusters of SMP PCs

2000 / IEEE / 0-7695-0550-3
By: Cappello, F.; Etiemble, D.; Richard, O.;

Gate stack preparation with high-k materials in a cluster tool

2001 / IEEE / 0-7803-6731-6
By: Tuominen, M.; Maes, J.W.; Caymax, M.; Vandervorst, W.; De Gendt, S.; Hohira, H.; Conard, T.; Heyns, M.; Richard, O.;

Physical characterisation of high-k gate stacks deposited on HF-last surfaces

2001 / IEEE / 4-89114-021-6
By: Bender, H.; Conard, T.; Tsai, W.; Kluth, J.; Chen, J.; De Gendt, S.; Caymax, M.; Vandervorst, W.; Maes, J.W.; Detavernier, C.; Besling, W.; Brijs, B.; Zhao, C.; Richard, O.; Petry, J.; Nohira, H.;

Infrared interface analysis of high-k dielectrics deposited by atomic layer chemical vapour deposition

2001 / IEEE / 4-89114-021-6
By: Cosnier, V.; Chabli, A.; Caymax, A.; Chen, J.; Conard, T.; Nohira, H.; Richard, O.; Tsai, W.; Vandervorst, W.; Young, E.; Zhao, C.; De Gendt, S.; Heyns, A.; Maes, J.W.H.; Tuominen, M.; Rochat, N.; Olivier, M.; Bender, H.;

The virtual cluster: a dynamic network environment for exploitation of idle resources

2002 / IEEE / 0-7695-1772-2
By: Richard, B.; Richard, O.; Novaes, R.; Saikoski, K.; Maillard, N.; Blanco, F.; De Rose, C.;

Physical characterization of ultrathin high k dielectrics

2003 / IEEE / 0-7803-7747-8
By: Vandervorst, W.; Brijs, B.; Bender, H.; Conard, O.T.; Petry, J.; Richard, O.; Van Elshocht, S.; Delabie, A.; Caymax, M.; De Gendt, S.; Cosnier, V.; Green, M.; Chen, J.;

Scaling of high-k dielectrics towards sub-1nm EOT

2003 / IEEE / 0-7803-7765-6
By: Heyns, M.; Beckx, S.; Bender, H.; Blomme, P.; Boullart, W.; Brijs, B.; Carter, R.; Caymax, M.; Claes, M.; Conard, T.; De Gendt, S.; Degraeve, R.; Delabie, A.; Deweerdt, W.; Groeseneken, G.; Henson, K.; Kauerauf, T.; Kubicek, S.; Lucci, L.; Lujan, G.; Mentens, J.; Pantisano, L.; Petry, J.; Richard, O.; Rohr, E.; Schram, T.; Vandervorst, W.; Van Doorne, P.; Van Elshocht, S.; Westlinder, J.; Witters, T.; Zhao, C.; Cartier, E.; Chen, J.; Cosnier, V.; Green, M.; Jang, S.E.; Kaushik, V.; Kerber, A.; Kluth, J.; Lin, S.; Tsai, W.; Young, E.; Manabe, Y.; Shimamoto, Y.; Bajolet, P.; De Witte, H.; Maes, J.W.; Date, L.; Pique, D.; Coenegrachts, B.; Vertommen, J.; Passefort, S.;

New low-stress PECVD poly-SiGe Layers for MEMS

2003 / IEEE
By: Rusu, C.; Otter, B.; Leca, V.; Kronmuller, S.; Fischer, F.; Larmer, F.; Witvrouw, A.; Geenen, L.; Brijs, B.; Richard, O.; Verbist, A.; Parmentier, B.; Sedky, S.;

Physical characterization of HfO/sub 2/ deposited on Ge substrates by MOCVD

2003 / IEEE / 0-7803-8139-4
By: Onsia, B.; Meuris, M.; Kubicek, S.; De Gendt, S.; Conard, T.; Caymax, M.; Richard, O.; Van Elshocht, S.; Heyns, M.; Zhao, C.; Brijs, B.; Van Steenbergen, J.; Teerlinck, I.;

Triple junctions for reduced impact of offset spacer variation on CMOS device parameters

2004 / IEEE / 0-7803-8478-4
By: Richard, O.; Henson, K.; Kunnen, E.; De Keersgieter, A.; Rooyackers, R.; Jurczak, M.; Dachs, C.;

Fully-integrated WCDMA direct conversion SiGeC BiCMOS receiver

2004 / IEEE / 0-7803-8618-3
By: Pellat, B.; Blanc, J.-P.; Garcia, P.; Belot, D.; Szelag, B.; Conti, P.; Richard, O.; Reaute, F.; Majcherczak, S.; Thevenet, D.; Goussin, F.; Baud, L.; Knopik, V.; Persechini, P.;

45 nm nMOSFET with metal gate on thin SiON driving 1150 /spl mu/A//spl mu/m and off-state of 10nA//spl mu/m

2004 / IEEE / 0-7803-8684-1
By: Cubaynes, F.N.; Hooker, J.C.; Boullart, W.; Coenegrachts, B.; Vertommen, J.; Richard, O.; Bender, H.; Vandervorst, W.; Kaiser, M.; Everaert, J.-L.; Jurczak, M.; Biesemans, S.; Beckx, S.; Tokei, Z.; Schram, T.; Deweerd, W.; Kaczer, B.; Dachs, C.J.J.; Demand, M.; Lander, R.J.P.; Henson, K.;

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

2005 / IEEE / 4-900784-00-1
By: Brus, S.; Maex, K.; Vrancken, C.; Jurczak, M.; Pawlak, M.A.; Richard, O.; Chiarella, T.; van Dal, M.J.H.; Niwa, M.; Kubicek, S.; Demeurisse, C.; Anil, K.G.; Lauwers, A.; Veloso, A.; Kittl, J.A.; Biesemans, S.;

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

2005 / IEEE / 4-900784-00-1
By: Anil, K.G.; Verheyen, P.; Biesemans, S.; Jurczak, M.; Absil, P.; De Meyer, K.; Boullart, W.; Beckx, S.; Kubicek, S.; Veloso, A.; Richard, O.; van Dal, M.; Kittl, J.A.; Goodwin, M.; Lauwers, A.; Yim, Y.S.; Brus, S.; Mannaert, G.; Rooyackers, R.; Shi, X.; Degroote, B.; Locorotondo, S.; Vos, R.; Snow, J.; Kaczer, B.; Dixit, A.; Collaert, N.;

Role of dielectric and barrier integrity in reliability of sub-100 nm copper low-k interconnects

2005 / IEEE / 0-7803-8803-8
By: Maex, K.; Beyer, G.P.; Travaly, Y.; Richard, O.; Tokei, Z.; Escorcia, O.; Waldfried, C.; Van Aelst, J.; Roussel, P.;

Towards optimally shaped fins in p-channel tri-gate FETs: can fin height be reduced further?

2005 / IEEE / 0-7803-9058-X
By: Rooyackers, R.; Richard, O.; Bros, S.; Mercha, A.; Collaert, N.; Jurczak, M.; Anil, K.G.; Dixit, A.; Goodwin, M.; De Meyer, K.;

Low-damage damascene patterning of SiOC(H) low-k dielectrics

2005 / IEEE / 0-7803-8752-X
By: Travaly, Y.; Richard, O.; Iacopi, F.; Van Olmen, J.; Van Hove, M.; Struyf, H.; Vanhaelemeersch, S.; Hendrickx, D.; Boullart, W.;

High transmission performance integrated antennas on SOI substrate for VLSI wireless interconnects

2005 / IEEE / 0-7803-8752-X
By: Exshaw, O.; Torres, J.; Benech, P.; Ndagijimana, F.; Tinella, C.; Farcy, A.; Triantafyllou, A.; Raynaud, C.; Richard, O.;

CD SEM calibration to TEM for accurate metrology of fins in MuGFET devices

2005 / IEEE / 0-7803-9143-8
By: Degroote, B.; Jurczak, M.; Pollentier, I.; Cheng, S.; Ercken, M.; Rooyackers, R.; Collaert, N.; Lorusso, G.F.; Long, T.; Prochazka, J.; Shirke, S.; Kuppa, R.; Azordegan, A.; Bender, H.; Richard, O.; Biesemans, S.;

Grid'5000: a large scale and highly reconfigurable grid experimental testbed

2005 / IEEE / 0-7803-9492-5
By: Caron, E.; Dayde, M.; Cappello, F.; Richard, O.; Quetier, B.; Namyst, R.; Mornet, G.; Melab, N.; Leduc, J.; Lanteri, S.; Jeannot, E.; Primet, P.; Jegou, Y.; Desprez, F.;

A batch scheduler with high level components

2005 / IEEE / 0-7803-9074-1
By: Neyron, P.; Da Costa, G.; Capit, N.; Richard, O.; Georgiou, Y.; Mounie, G.; Martin, C.; Huard, G.;

0.13/spl mu/m CMOS SOI SP6T antenna switch for multi-standard handsets

2006 / IEEE / 0-7803-9472-0
By: Majcherczak, S.; Reaute, F.; Cathelin, A.; Richard, O.; Tinella, C.; Belot, D.; Blanchet, F.;

Resources availability for peer to peer systems

2006 / IEEE / 0-7695-2466-4
By: Marchand, C.; Da Costa, G.; Vincent, J.-M.; Richard, O.;

A tool for environment deployment in clusters and light grids

2006 / IEEE / 1-4244-0054-6
By: Leduc, J.; Georgiou, Y.; Richard, O.; Peyrard, J.; Videau, B.;

Lightweight emulation to study peer-to-peer systems

2006 / IEEE / 1-4244-0054-6
By: Richard, O.; Nussbaum, L.;

Understanding integration damage to low-k films: mechanisms and dielectric behaviour at 100kHz and 4GHz

2006 / IEEE / 1-4244-0104-6
By: Travaly, Y.; Bender, H.; Schwartz, A.R.; Scherz, A.; Mannaert, G.; Talanov, V.V.; Brongersma, S.H.; Van Aelst, J.; Richard, O.; Iacopi, F.; Beyer, G.; Moinpour, M.; Antonelli, G.A.;

Low-k properties and integration processes enabling reliable interconnect scaling to the 32 nm technology node

2006 / IEEE / 1-4244-0104-6
By: Ikeda, A.; Van Hove, M.; Beyer, G.; Ciofi, I.; Sprey, H.; Matsuki, N.; Fukazawa, A.; Kemeling, N.; Verheyden, G.; Weemaes, R.G.R.; Kaiser, M.; Bender, H.; Richard, O.; Carbonell, L.; Heylen, N.; Versluijs, J.; Struyf, H.; Van Aelst, J.; Hendrickx, D.; Willegems, M.; Bruynseraede, C.; Michelon, J.; Iacopi, F.; Tokei, Zs.; Li, Y.L.; Hoofman, R.J.O.M.; Humbert, A.; Travaly, Y.;

Dual Work Function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe Cap

2006 / IEEE / 1-4244-0005-8
By: Sijmus, B.; Tigelaar, H.; Kauerauf, T.; Vrancken, C.; Shickova, A.; Locorotondo, S.; de Marneffe, J.-F.; Brus, S.; Lauwers, A.; Hoffmann, T.; Veloso, A.; Kittl, J.A.; Biesemans, S.; Jurczak, M.; Absil, P.; Niwa, M.; Bender, H.; Richard, O.; Chiarella, T.; Kerner, C.; Kubicek, S.; Demeurisse, C.; Yu, H.Y.; Pawlak, M.A.;

Electrical Properties of nMOSFETs Using the NiSi:Yb FUSI Electrode

2007 / IEEE
By: Opsomer, K.; Mertens, S.; Richard, O.; Demeurisse, C.; Lauwers, A.; Singanamalla, R.; Biesemans, S.; Yu, H.Y.; Absil, P.; Rosseel, E.;

Polycrystalline Si optimization for 45nm node Ni-FUSI gate

2006 / IEEE / 1-4244-0161-5
By: Schaekers, M.; Shi, X.; Date, L.; Rosseel, E.; Brus, S.; Richard, O.; Moussa, A.; Everaert, J.L.; Rothschild, A.;

Metal Gate Technology using a Dy2O3 Dielectric Cap Approach for multiple-VT in NMOS FinFETs

2007 / IEEE / 978-1-4244-0879-5
By: Collaert, N.; San, K.T.; Witters, L.; Son, N.J.; Ferain, I.; Jurczak, M.; Biesemans, S.; De Meyer, K.; Onsia, B.; Lehnen, P.; Van Elshocht, S.; Bender, H.; Richard, O.; Favia, P.; Adelmann, C.; Kauerauf, T.; Kaczer, B.;

Impact of sub-melt laser annealing on Si1-xGex source /drain defectivity

2007 / IEEE / 978-1-4244-1227-3
By: Felch, S.B.; McIntosh, R.; Absil, P.; Loo, R.; Bender, H.; Geypen, J.; Schreutelkamp, R.; Richard, O.; Hoffmann, T.; Verheyen, P.; Hikavyy, A.; Lu, J.P.; Rosseel, E.;

Evaluations of the Lightweight Grid CIGRI upon the Grid5000 Platform

2007 / IEEE / 0-7695-3064-8
By: Capit, N.; Richard, O.; Georgiou, Y.;

An efficient methodology for Electrical Monitoring in manufacturing environment

2008 / IEEE / 978-1-4244-1964-7
By: Grolier, J.L.; Chauvet, A.; Tran, A.; Degand, F.; Saout, D.; Domart, F.; Richard, O.;

Key factors to sustain the extension of a MHM-based integration scheme to medium and high porosity PECVD low-k materials

2008 / IEEE / 978-1-4244-1911-1
By: Travaly, Y.; van Aelst, J.; Beyer, G.; Sprey, H.; Kobayashi, N.; Matsushita, K.; Baklanov, M.; Struyf, H.; Kaneko, S.; Beynet, J.; van Cauwenberghe, M.; Kesters, E.; Le, Q. T.; Truffert, V.; Verdonck, P.; Dupont, T.; Camerotto, E.; Richard, O.; Bender, H.; Kroes, C.; de Roest, D.; Vereecke, G.; Claes, M.;

Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs

2008 / IEEE / 978-1-4244-1802-2
By: Witters, L.; Demand, M.; Veloso, A.; Jurczak, M.; Biesemans, S.; De Meyer, K.; Collaert, N.; Van Elshocht, S.; Rooyackers, R.; Vos, R.; Conard, T.; Bender, H.; Richard, O.; Brus, S.; Adelmann, C.; Kauerauf, T.; Simoen, E.; Roussel, P.J.; Kaczer, B.; Son, N.J.; Ferain, I.;

Capping-metal gate integration technology for multiple-VT CMOS in MuGFETs

2008 / IEEE / 978-1-4244-1954-8
By: Son, N.J.; Kaczer, B.; Ferain, I.; Demand, M.; Witters, L.; Veloso, A.; Jurczak, M.; Biesemans, S.; De Meyer, K.; Collaert, N.; Van Elshocht, S.; Rooyackers, R.; Vos, R.; Conard, T.; Bender, H.; Richard, O.; Brus, S.; Adelmann, C.; Roussel, P.J.;

Full-field EUV and immersion lithography integration in 0.186�m² FinFET 6T-SRAM cell

2008 / IEEE / 978-1-4244-2377-4
By: Veloso, A.; Demuynck, S.; Ercken, M.; Goethals, A.M.; Demand, M.; de Marneffe, J.-F.; Altamirano, E.; De Keersgieter, A.; Delvaux, C.; De Backer, J.; Brus, S.; Hermans, J.; Baudemprez, B.; Van Roey, F.; Lorusso, G.F.; Baerts, C.; Goossens, D.; Vrancken, C.; Mertens, S.; Versluijs, J.J.; Truffert, V.; Huffman, C.; Laidler, D.; Heylen, N.; Ong, P.; Parvais, B.; Rakowski, M.; Verhaegen, S.; Hikavyy, A.; Meiling, H.; Hultermans, B.; Romijn, L.; Pigneret, C.; Lok, S.; Van Dijk, A.; Shah, K.; Noori, A.; Gelatos, J.; Arghavani, R.; Schreutelkamp, R.; Boelen, P.; Richard, O.; Bender, H.; Witters, L.; Collaert, N.; Rooyackers, R.; Absil, P.; Lauwers, A.; Jurczak, M.; Hoffmann, T.; Vanhaelemeersch, S.; Cartuyvels, R.; Ronse, K.; Biesemans, S.;

The GREEN-NET framework: Energy efficiency in large scale distributed systems

2009 / IEEE / 978-1-4244-3751-1
By: Georgiou, Y.; Gelas, J.-P.; Da Costa, G.; Sharma, K.; Lefevre, L.; Richard, O.; Pierson, J.-M.; Orgerie, A.-C.;

Junction anneal sequence optimization for advanced high-k / metal gate CMOS technology

2009 / IEEE / 978-1-4244-3319-3
By: Favia, P.; Richard, O.; Rosseel, E.; Okuno, Y.; Chiarella, T.; Kerner, C.; Ragnarsson, L.-A.; Ortolland, C.; Hoffmann, T.; Schreutelkamp, R.; Biesemans, S.; Absil, P.P.; Kubicek, S.; Schram, T.; Everaert, J.-L.;

Optimized ultra-low thermal budget process flow for advanced High-K / Metal gate first CMOS using laser-annealing technology

2006 / IEEE / 978-1-4244-3308-7
By: Ortolland, C.; Ragnarsson, L.-A.; Hoffmann, T.; Biesemans, S.; Absil, P.P.; Cho, M.J.; Aoulaiche, M.; Kubicek, S.; Schram, T.; Everaert, J.-L.; Tseng, J.; Akheyar, A.; Okuno, Y.; Rosseel, E.; Chiarella, T.; Kerner, C.; Richard, O.; Favia, P.;

O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory

2009 / IEEE / 978-1-4244-4351-2
By: Van Houdt, J.; Kittl, J.A.; Debusschere, I.; Cacciato, A.; Jurczak, M.; Franquet, A.; Conard, T.; Richard, O.; Van den bosch, G.; Breuil, L.; Rothschild, A.; Schreutelkamp, R.; Boelen, P.; Date, L.; Ganguly, U.;

8�Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

2010 / IEEE / 978-1-4244-5450-1
By: Absil, P.; Biesemans, S.; Bender, H.; Richard, O.; Schram, T.; Rohr, E.; Wang, W.E.; Tseng, J.; Franco, J.; Crabbe, Y.; Kerner, C.; Loo, R.; Ragnarsson, L.-A.; Chiarella, T.; Cho, M.; Shamiryan, D.; Hikavyy, A.; Yamaguchi, S.; Takeoka, S.; Witters, L.; Hoffmann, T.;

Investigation of rare-earth aluminates as alternative trapping materials in Flash memories

2010 / IEEE / 978-1-4244-6661-0
By: Cacciato, A.; Van Houdt, J.; Kittl, J.A.; Debusschere, I.; Jurczak, M.; Bender, H.; Breuil, L.; Van Den Bosch, G.; Rothschild, A.; Swerts, J.; Adelmann, C.; Arreghini, A.; Richard, O.; Suhane, A.;

A 65nm CMOS fully integrated transceiver module for 60GHz wireless HD applications

2011 / IEEE / 978-1-61284-302-5
By: Ferragut, R.; Dehos, C.; Chaix, F.; Mounet, C.; Martineau, B.; Richard, O.; Siligaris, A.; Vincent, P.; Belot, D.; Cathelin, A.; Busson, P.; Pilard, R.; Yamamoto, S.D.; Dussopt, L.; Lanteri, J.;

Novel Bi-Layer Poly-Silicon Channel Vertical Flash Cell for Ultrahigh Density 3D SONOS NAND Technology

2011 / IEEE / 978-1-4577-0226-6
By: Blomme, P.; Van Houdt, J.; Cacciato, A.; Van den bosch, G.; Kar, G.S.; Baojung Tang; Van Aerde, S.; Arreghini, A.; Debusschere, I.; Richard, O.; Douhard, B.; Vrancken, C.; Paraschiv, V.; De Keersgieter, A.; Breuil, L.;