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Author: Pullini, A.

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NoC Design and Implementation in 65nm Technology

2007 / IEEE / 0-7695-2773-6
By: Atienza, D.; Meloni, P.; Angiolini, F.; Pullini, A.; Srinivasan Murali; Benini, L.; De Micheli, G.; Raffo, L.;

Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes

2005 / IEEE / 1-59593-174-0
By: Pullini, A.; Benini, L.; Bertozzi, D.; Angiolini, F.;

Bringing NoCs to 65 nm

2007 / IEEE
By: Angiolini, F.; Pullini, A.; Benini, L.; De Micheli, G.; Atienza, D.; Murali, S.;

A Scalable Algorithmic Framework for Row-Based Power-Gating

2008 / IEEE / 978-3-9810801-3-1
By: Macii, A.; Sathanur, A.; Poncino, M.; Benini, L.; Macii, E.; Pullini, A.;

Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis

2009 / IEEE / 978-1-4244-3781-8
By: Atienza, D.; Pullini, A.; Jie Zhang; Bobba, S.; De Micheli, G.;

A floorplan-aware interactive tool flow for NoC design and synthesis

2009 / IEEE / 978-1-4244-4940-8
By: Angiolin, F.; Reza Kakoee, M.; Benini, L.; Seiculescu, C.; Pullini, A.; Murali, S.;

Timing-driven row-based power gating

2007 / IEEE / 978-1-59593-709-4
By: Macii, E.; Macii, A.; Benini, L.; Pullini, A.; Sathanur, A.; Poncino, M.;

Networks on Chips: From research to products

2010 / IEEE / 978-1-4503-0002-5
By: Murali, S.; Seiculescu, C.; De Micheli, G.; Pullini, A.; Angiolini, F.; Benini, L.;

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

2011 / IEEE
By: Van der Plas, G.; Marchal, P.; Loi, I.; Mercha, A.; Oprins, H.; Torregiani, C.; Thijs, S.; Linten, D.; Stucchi, M.; Katti, G.; Velenis, D.; Cherman, V.; Vandevelde, B.; Simons, V.; De Wolf, I.; Labie, R.; Perry, D.; Bronckers, S.; Minas, N.; Cupac, M.; Ruythooren, W.; Van Olmen, J.; Phommahaxay, A.; de Potter de ten Broeck, M.; Opdebeeck, A.; Rakowski, M.; De Wachter, B.; Dehan, M.; Nelis, M.; Agarwal, R.; Pullini, A.; Angiolini, F.; Benini, L.; Dehaene, W.; Travaly, Y.; Beyne, E.; Limaye, P.;

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