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Author: Lindert, N.

Results

Integration of a 3-D capacitor into a logic interconnect stack for high performance embedded DRAM SoC technology
2014 / IEEE
By: Brain, R.; Bisnik, N.; Zhang, K.; Wang, Y.; Rockford, L.; Peach, J.; Lindert, N.; Neulinger, J.; Chen, H.-P.;
Comparison of GIDL in p/sup +/-poly PMOS and n/sup +/-poly PMOS devices
1996 / IEEE
By: Chenming Hu; Wann, C.; Yoshida, M.; Lindert, N.;
Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages
1999 / IEEE
By: Chenming Hu; Tang, S.; Sugii, T.; Lindert, N.;
A bulk-Si-compatible ultrathin-body SOI technology for sub-100 nm MOSFETs
1999 / IEEE / 0-7803-5170-3
By: Cao, K.; McHale, J.; Su, Y.; Lindert, N.; Tam, H.; King, T.-J.; Kedzierski, J.; Subramanian, V.; Hu, C.; Bokor, J.;
Ultra-thin body SOI MOSFET for deep-sub-tenth micron era
1999 / IEEE / 0-7803-5410-9
By: Lindert, N.; Asano, K.; Yang-Kyu Choi; Chenming Hu; Bokor, J.; Tsu-Jae King; Subramanian, V.;
Ultrathin-body SOI MOSFET for deep-sub-tenth micron era
2000 / IEEE
By: Bokor, J.; Tsu-Jae King; Subramanian, V.; Lindert, N.; Asano, K.; Yang-Kyu Choi; Chenming Hu;
FinFET-a quasi-planar double-gate MOSFET
2001 / IEEE / 0-7803-6608-5
By: Xuejue Huang; Wen-Chin Lee; Chang, L.; Yang-Kyu Choi; Lindert, N.; Subramanian, V.; Tang, S.H.; Chenming Hu; Tsu-Jae King; Bokor, J.;
Quasi-planar NMOS FinFETs with sub-100 nm gate lengths
2001 / IEEE / 0-7803-7014-7
By: Anderson, E.; Leland Chang; Yang-Kyu Choi; Lindert, N.; Wenchin Lee; Chenming Hu; Bokor, J.; Tsu-Jae King;
Sub-60-nm quasi-planar FinFETs fabricated using a simplified process
2001 / IEEE
By: Chang, L.; Lindert, N.; Chenming Hu; Bokor, J.; Yang-Kyu Choi; Tsu-Jae King; Wen-Chin Lee; Anderson, E.H.;
Quasi-planar FinFETs with selectively grown germanium raised source/drain
2001 / IEEE / 0-7803-6739-1
By: King, T.-J.; Lee, W.-C.; Anderson, E.; Chang, L.; Bokor, J.; Lindert, N.; Choi, Y.-K.; Hu, C.;
Moore's law lives on [CMOS transistors]
2003 / IEEE
By: Chenming Hu; Bokor, J.; Lindert, N.; Peiqi Xuan; Tsu-Jae King; Kedzierski, J.; Yang-Kyu Choi; Leland Chang;
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell
2004 / IEEE / 0-7803-8684-1
By: Bai, P.; Bohr, M.; Auth, C.; Balakrishnan, S.; Bost, M.; Brain, R.; Chikarmane, V.; Heussner, R.; Hussein, M.; Hwang, J.; Ingerly, D.; James, R.; Jeong, J.; Kenyon, C.; Lee, E.; Lee, S.-H.; Lindert, N.; Liu, M.; Ma, Z.; Marieb, T.; Murthy, A.; Nagisetty, R.; Natarajan, S.; Neirynck, J.; Ott, A.; Parker, C.; Sebastian, J.; Shaheed, R.; Sivakumar, S.; Steigerwald, J.; Tyagi, S.; Weber, C.; Woolery, B.; Yeoh, A.; Zhang, K.;
A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors
2005 / IEEE / 0-7803-9268-X
By: Jan, C.-H.; Bai, P.; Holt, B.; Bohr, M.; Zhang, Y.; Zhang, K.; Young, I.; Yip, J.; Wei, L.; Wang, Y.; Turkot, B.; Sacks, G.; Roskowski, A.; Rockford, L.; Reese, P.; Ramey, S.; Patel, M.; Post, I.; Park, J.; Packan, P.; Neirynck, J.; Natarajan, S.; Lio, A.; Lindert, N.; Lin, J.; Choi, J.; Curello, G.; Jacobs, S.; Jeong, J.; Johnson, K.; Jones, D.; Klopcic, S.;
An advanced low power, high performance, strained channel 65nm technology
2005 / IEEE / 0-7803-9268-X
By: Tyagi, S.; Tone, K.; St Amour, A.; Sivakumar, S.; Sell, B.; Sebastian, J.; Parker, C.; Natarajan, S.; Nagisetty, R.; Liu, M.; Lindert, N.; Lee, S.-H.; Kenyon, C.; James, R.; Heussner, R.; Golonzka, O.; Gannavaram, S.; Deshpande, H.; Curello, G.; Bai, P.; Auth, C.;
A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications
2006 / IEEE / 1-4244-0438-X
By: Jalan, U.; Komeyii, K.; Hafez, W.; Gannavaram, S.; Curello, G.; Akbar, M.; Post, I.; Jan, C.-H.; Bai, P.; Yeh, D.; Tsai, C.; Sacks, G.; Rizk, J.; Park, J.; Lindert, N.; Lin, J.;
A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors
2008 / IEEE / 978-1-4244-2377-4
By: Jan, C.-H.; Bai, P.; Mistry, K.; Yip, J.; Yeh, J.-Y.; Yang, L.; Wang, Y.; Tsai, C.; Towner, D.; Tashiro, H.; Sacks, G.; Rizk, J.; Prince, M.; Prasad, C.; Pradhan, N.; Post, I.; Pei, L.; Parker, R.; Park, J.; Olson, S.; Naskar, S.; Mezhiba, A.; Komeyli, K.; Biswas, S.; Buehler, M.; Chen, Z.-P.; Curello, G.; Gannavaram, S.; Hafez, W.; He, J.; Hicks, J.; Jalan, U.; Lazo, N.; Lin, J.; Lindert, N.; Litteken, C.; Jones, M.; Kang, M.;
A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications
2009 / IEEE / 978-1-4244-5641-3
By: Jan, C.-H.; Agostinelli, M.; Buehler, M.; Chen, Z.-P.; Choi, S.-J.; Curello, G.; Deshpande, H.; Gannavaram, S.; Hafez, W.; Jalan, U.; Kang, M.; Kolar, P.; Komeyli, K.; Landau, B.; Lake, A.; Lazo, N.; Lee, S.-H.; Leo, T.; Lin, J.; Lindert, N.; Ma, S.; McGill, L.; Meining, C.; Paliwal, A.; Park, J.; Phoa, K.; Post, I.; Pradhan, N.; Prince, M.; Rahman, A.; Rizk, J.; Rockford, L.; Sacks, G.; Schmitz, A.; Tashiro, H.; Tsai, C.; Vandervoorn, P.; Xu, J.; Yang, L.; Yeh, J.-Y.; Yip, J.; Zhang, K.; Zhang, Y.; Bai, P.;
A 32nm low power RF CMOS SOC technology featuring high-k/metal gate
2010 / IEEE / 978-1-4244-5450-1
By: VanDerVoorn, P.; Agostinelli, M.; Jan, C.; Bai, P.; Yip, J.; Yeh, J.; Young, I.; Yang, L.; Xu, J.; Xu, H.; Tsai, C.; Taylor, S.; Tashiro, H.; Soumyanath, K.; Sacks, G.; Rockford, L.; Rizk, J.; Rahman, A.; Phoa, K.; Park, J.; Mudanai, S.; Choi, S.; Curello, G.; Deshpande, H.; El-Tanani, M.A.; Hafez, W.; Jalan, U.; Janbay, L.; Kang, M.; Koh, K.; Komeyli, K.; Lakdawala, H.; Lin, J.; Lindert, N.;

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