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Author: Hsin-Hsiung Huang

Results

Timing- and interference-free multi-layer routing tree
2011 / IEEE / 978-1-61284-857-0
By: Tsai-Ming Hsieh; Hsin-Hsiung Huang; Pi-Hua Su;
Structural decomposition with functional considerations for low power
2002 / IEEE / 0-7695-1561-4
By: Chih-Hung Lee; Tsai-Ming Hsieh; Hsin-Hsiung Huang; Yu-Chung Lin;
A new congestion and crosstalk aware router
2005 / IEEE / 0-7803-8834-8
By: Yung-Ching Chen; Chin-Hui Wang; Hsin-Hsiung Huang; Chih-Hung Lee; Tsai-Ming Hsieh;
Congestion-driven floorplanning by adaptive modular shaping
2005 / IEEE / 0-7803-9197-7
By: Chih-Yuan Lin; Chung-Chiao Chang; Hsin-Hsiung Huang; Chih-Hung Lee; Tsai-Ming Hsieh;
A congestion-driven buffer planner with space reservation
2006 / IEEE / 0-7803-9389-9
By: Tsai-Ming Hsieh; Yung-Ching Chen; Hsin-Hsiung Huang;
Partition-based Routing Tree Algorithm with Obstacles
2007 / IEEE / 978-1-4244-0796-5
By: Tsai-Ming Hsieh; Hui-Yu Huang; Yu-Cheng Lin; Hsin-Hsiung Huang;
Timing-Driven Steiner Tree Construction among the Obstacles
2007 / IEEE / 978-1-4244-0796-5
By: Shu-Ping Chang; Hsin-Hsiung Huang; Hi-Cheng Lin;
Large-scale timing-driven rectilinear steiner tree construction in presence of obstacles
2007 / IEEE / 978-1-4244-1175-7
By: Tung-Fu Chiu; Hsin-Hsiung Huang; Tsai-Ming Hsieh; Yu-Cheng Lin;
Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system
2008 / IEEE / 978-1-4244-1683-7
By: Hui-Yu Huang; Hsin-Hsiung Huang; Tsai-Ming Hsieh; Yu-Cheng Lin;
Timing-driven X-architecture router among rectangular obstacles
2008 / IEEE / 978-1-4244-1683-7
By: Tsai-Ming Hsieh; Yu-Cheng Lin; Shu-Ping Chang; Hsin-Hsiung Huang;
Obstacle-avoiding electromigration aware wire planning for analog circuits
2009 / IEEE / 978-9-8108-2468-6
By: His-An Chien; Hsin-Hsiung Huang; Cheng-Chiang Lin; Tsai-Ming Hsieh;
ILP-based optimal multi-threshold voltages assignment under performance constraints
2009 / IEEE / 978-9-8108-2468-6
By: Hsin-Hsiung Huang; His-An Chien; Chun-Hua Chung; Tsai-Ming Hsieh;

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