Your Search Results

Use materials by this author in your textbook!

AcademicPub holds over eight million pieces of educational content such as case studies and journal articles for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!

Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

Author: Greiner, A.

Results

Particle swarm optimization on a new parametric model of a deformable membrane lens

2011 / IEEE / 978-1-4577-0336-2
By: Strohmeier, D.; Korvink, J.G.; Wallrabe, U.; Greiner, A.; Domaszewski, M.; Draheim, J.;

Top-down vs. bottom-up coarse-graining of graphene and CNTs for nanodevice simulation

2012 / IEEE / 978-1-4673-1124-3
By: Kauzlaric, D.; Korvink, J.G.; Succi, S.; Greiner, A.; Espa� P.; Hanein, Y.; Liba, O.;

Electrowetting droplets investigated with smoothed particle hydrodynamics and moving least squares

2012 / IEEE / 978-1-4673-1124-3
By: Lienemann, J.; Greiner, A.; Weiss, D.; Korvink, J.G.;

On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures

2014 / IEEE
By: Benabdenbi, M.; Greiner, A.; Refauvelet, D.; Zhang, Z.; Pecheux, F.;

NOISY: an electrical noise checker for ULSI

1988 / IEEE / 0-8186-0869-2
By: Murzin, J.; Marbot, R.; Guillemet, M.; Greiner, A.; Gourdy, F.;

TAS: an accurate timing analyser for CMOS VLSI

1991 / IEEE
By: Greiner, A.; Marbot, R.; Hajjar, A.; Kiani, P.;

GENVIEW: a portable source-level debugger for macrocell generators

1991 / IEEE
By: Pecheux, F.; Greiner, A.; Compan, A.; Petrot, F.;

DESB, a functional abstractor for CMOS VLSI circuits

1992 / IEEE / 0-8186-2780-8
By: Greiner, A.; Laurentin, M.; Marbot, R.;

Application of a redefinable symbolic simulation technique in VLSI testability design rules checking

1994 / IEEE / 0-8186-5620-4
By: Greiner, A.; Florent, O.; Hirech, M.; Rejouan, E.;

Designing portable module generators using the Alliance CAD system

1994 / IEEE / 0-8186-5320-5
By: Greiner, A.; Petrot, F.;

Encapsulating networks and routing

1994 / IEEE / 0-8186-5602-6
By: Greiner, A.; Blin, J.M.; Zerrouk, B.;

RAPID-2, an object-oriented associative memory applicable to genome data processing

1994 / IEEE / 0-8186-5090-7
By: Greiner, A.; Faudemay, P.; Archambaud, D.;

Multilevel logic synthesis of very high complexity circuits

1994 / IEEE / 0-8186-5410-4
By: Pradho, E.; Greiner, A.; Dictus, N.; Burgun, L.; Sarwary, C.;

A redefinable symbolic simulation technique for testability design rules checking

1994 / IEEE / 0-8186-5410-4
By: Rejouan, E.; Greiner, A.; Floret, O.; Hirech, M.;

Design of a high complexity superscalar microprocessor with the portable IDPS ASIC library

1994 / IEEE / 0-8186-5410-4
By: Winckel, L.; Wajsburt, F.; Lucas, L.; Greiner, A.;

A high density datapath compiler mixing random logic with optimized blocks

1993 / IEEE / 0-8186-3410-3
By: Greiner, A.; Ammar, L.B.;

A public domain high performances portable ROM generator

1994 / IEEE / 0-8186-6430-4
By: Greiner, A.; Petrot, F.;

Designing a high complexity microprocessor using the Alliance CAD system

1994 / IEEE / 0-7803-2020-4
By: Wajsburt, F.; Lucas, L.; Greiner, A.;

FSM synthesis on FPGA architectures

1994 / IEEE / 0-7803-2020-4
By: Burgun, L.; Lopes, E.P.; Sarwary, G.; Greiner, A.;

A redefinable symbolic simulation technique to testability design rules checking

1994 / IEEE / 0-7803-1915-X
By: Hirech, M.; Rejouan, E.; Greiner, A.; Florent, O.;

A portable clock multiplier generator using digital CMOS standard cells

1996 / IEEE
By: Dioury, K.; Combes, M.; Greiner, A.;

On the design of mixed-mode simulators for modern VLSI circuits

1995 / IEEE / 0-7803-2972-4
By: Greiner, A.; Sabet, P.B.; Abdallah, N.;

Design methodology of a test chip for a portable 8ns 10 ports register file

1995 / IEEE / 0-7803-2584-2
By: Lucas, L.; Greiner, A.;

A high performance modular embedded ROM architecture

1995 / IEEE / 0-7803-2570-2
By: Greiner, A.; Duhalde, M.; Petrot, F.;

Er-doped integrated optical devices in LiNbO/sub 3/

1996 / IEEE
By: Baumann, I.; Bosso, S.; Brinkmann, R.; Corsini, R.; Dinand, M.; Wessel, R.; Schafer, K.; Sochtig, J.; Sohler, W.; Suche, H.; Greiner, A.;

RCube: a message routing device using the OMI/HIC high speed link technology

1996 / IEEE / 0-7803-3650-X
By: Zerrouk, B.; Nezamzadeh, R.; Marbot, R.; Derieux, A.; Greiner, A.; Potter, F.; Reibaldi, V.;

A simulation environment for core based embedded systems

1997 / IEEE / 0-8186-7934-4
By: Hommais, D.; Petrot, F.; Greiner, A.;

Cycle precise core based hardware/software system simulation with predictable event propagation

1997 / IEEE / 0-8186-8129-2
By: Hommais, D.; Petrot, F.; Greiner, A.;

Integrated optical Ti:Er:LiNbO/sub 3/ soliton source

1997 / IEEE
By: Sohler, W.; Wessel, R.; Qiu, W.; Greiner, A.; Suche, H.;

Influence Of Carrier Transport On The Turn-on Delay In A Separate Confinement Heterostructure Quantum Well Laser

1994 / IEEE / 0-7803-1789-0
By: Hansmam, S.; Hillmer, H.; Kuhn, T.; Greiner, A.; Burkhard, H.;

Extraction of noise parameters for the macromodelling of MEMS

1998 / IEEE / 0-7803-4909-1
By: Korvink, J.G.; Greiner, A.;

Diode Pumped And Packaged 10GHz Harmonically Modelocked TiEr:LiNbO/sub 3/-Waveguide Laser for Soliton Transmission

1997 / IEEE / 4-88552-187-4
By: Suche, H.; Qiu, W.; Greiner, A.; Wessel, R.; Sohler, W.;

YAGLE, a second generation functional abstractor for CMOS VLSI circuits

1998 / IEEE / 0-7803-4969-5
By: Lester, A.; Greiner, A.; Bazargan-Sabet, P.;

A generic architecture for on-chip packet-switched interconnections

2000 / IEEE / 0-7695-0537-6
By: Guerrier, P.; Greiner, A.;

Analog design for reuse-case study: very low-voltage /spl Delta//spl Sigma/ modulator

2001 / IEEE / 0-7695-0993-2
By: Greiner, A.; Louerai, M.-M.; Kaiser, A.; Dessouky, M.;

Volume shrinking in micro-fluidic self-assembly

2002 / IEEE / 0-7803-7276-X
By: Lienemann, J.; Korvink, J.G.; Greiner, A.;

Micro-network for SoC: implementation of a 32-port SPIN network

2003 / IEEE / 0-7695-1870-2
By: Greiner, A.; Andriahantenaina, A.;

SPIN: a scalable, packet switched, on-chip micro-network

2003 / IEEE / 0-7695-1870-2
By: Mortiez, L.; Greiner, A.; Charlery, H.; Adriahantenaina, A.; Zeferino, C.A.;

STEPS: experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores

2004 / IEEE / 0-7695-2085-5
By: Greiner, A.; Benabdenbi, M.; Tuna, M.; Viaud, E.; Pecheux, F.;

Fast cycle accurate simulator to simulate event-driven behavior

2004 / IEEE / 0-7803-8575-6
By: Petrot, F.; Buchmann, R.; Greiner, A.;

Physical design of the VCI wrappers for the on-chip packet-switched network named SPIN

2004 / IEEE / 0-7803-8656-6
By: Greiner, A.; Andriahantenaina, A.; Charlery, H.;

Efficient Pre-stressed Harmonic Analysis of RF-Microresonators by Means of Model Order Reduction

2006 / IEEE / 1-4244-0275-1
By: Gaddi, R.; Del Tin, L.; Korvink, J.G.; Greiner, A.; Rudnyi, E.; Gnudi, A.;

Mapping an obstacles detection, stereo vision-based, software application on a multi-processor system-on-chip

2006 / IEEE / 4-901122-86-X
By: Petrot, F.; Greiner, A.; Labayrade, R.; Chotin-Avot, R.; Benabdenbi, M.; Carrier, M.;

T-Proc: An Embedded IEEE1500-Wrapped Cores Tester

2006 / IEEE / 1-4244-0157-7
By: Greiner, A.; Benabdenbi, M.; Tuna, M.;

On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures

2006 / IEEE / 0-7695-2609-8
By: Greiner, A.; Petrot, F.; Gomez, P.;

A Systemc Test Environment For Spin Network

2006 / IEEE / 83-922632-2-7
By: Greiner, A.; Charlery, H.;

A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

2006 / IEEE / 1-4244-0390-1
By: Sheibanyrad, A.; Greiner, A.; Miro Panades, I.;

Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures

2007 / IEEE / 0-7695-2773-6
By: Miro Panades, I.; Greiner, A.;

At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester

2007 / IEEE / 0-7695-2812-0
By: Greiner, A.; Benabdenbi, M.; Tuna, M.;

Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture

2007 / IEEE / 978-3-9810801-2-4
By: Sheibanyrad, A.; Greiner, A.; Miro Panades, I.;

Non Linear Compact Modeling of RE-MEMS Switches by Means of Model Order Reduction

2007 / IEEE / 1-4244-0841-5
By: Greiner, A.; Rudnyi, E.B.; Gnudi, A.; Gaddi, R.; Iannacci, J.; Del Tin, L.; Korvink, J.G.;

A high flux continuous source of ultracold guided chromium atoms

2007 / IEEE / 978-1-4244-0930-3
By: Falkenau, M.; Aghajani-Talesh, A.; Sebastian, J.; Greiner, A.; Griesmaier, A.; Pfau, T.; Rehme, P.;

Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture

2008 / IEEE / 978-0-7695-3098-7
By: Vivet, P.; Clermidy, F.; Miro-Panades, I.; Greiner, A.;

A fully static scheduling approach for fast cycle accurate systemC simulation of MPSoCs

2007 / IEEE / 978-1-4244-1846-6
By: Buchmann, R.; Greiner, A.;

A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

2008 / IEEE / 978-1-60558-115-6
By: Taktak, S.; Greiner, A.; Zhen Zhang;

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

2008 / IEEE
By: Miro-Panades, I.; Greiner, A.; Sheibanyrad, A.;

A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCs

2009 / IEEE / 978-0-7695-3690-3
By: de Mello, A.V.; Becoulet, A.; Pouillon, N.; Greiner, A.; Pecheux, F.;

Multi-compartment: A new architecture for secure co-hosting on SoC

2009 / IEEE / 978-1-4244-4465-6
By: Greiner, A.; Schwarz, C.; Porquet, J.;

A generic hardware / software communication middleware for streaming applications on shared memory multi processor systems-on-chip

2009 / IEEE / 978-2-9530504-1-7
By: Pouillon, N.; Faure, E.; Greiner, A.; Genius, D.;

Modeling Surface Scattering Effects in the Solution of the BTE based on Spherical Harmonics Expansion

1996 / IEEE / 286332196X
By: Rudan, M.; Greiner, A.; Vecchi, M. C.;

Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations

2010 / IEEE / 978-3-9810801-6-2
By: Mello, A.; Pecheux, F.; Greiner, A.; Maia, I.;

A Flexible High Perfomance Serial Radix-2 FFT Butterfly Arithmetic Unit

1985 / IEEE
By: Greiner, A.; Neguez, G.; Mehrez, H.; Kara-Terki, C.;

A Low-Cost Electromagnetic Generator for Vibration Energy Harvesting

2011 / IEEE
By: Greiner, A.; Bouendeu, E.; Korvink, J.G.; Smith, P.J.;

Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components

2010 / IEEE / 978-1-4244-7723-4
By: Greiner, A.; Zhen Zhang; Benabdenbi, M.;

Parallel TLM simulation of MPSoC on SMP workstations: Influence of communication locality

2010 / IEEE / 978-1-61284-151-9
By: Pessoa, I.M.; Pecheux, F.; Greiner, A.; Mello, A.;

Design Synthesis of Electromagnetic Vibration-Driven Energy Generators Using a Variational Formulation

2011 / IEEE
By: Korvink, J.G.; Smith, P.J.; Greiner, A.; Bouendeu, E.;

NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCs

2011 / IEEE / 978-3-9810801-8-6
By: Schwarz, C.; Greiner, A.; Porquet, J.;

Return To Top