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Author: Chunhong Chen

Results

Low power SET-based SRAM cell design using negative differential conductance
2011 / IEEE / 978-1-4577-1516-7
By: Chunhong Chen; Syed, N.;
A hybrid CMOS-SET multiplier using frequency modulation
2011 / IEEE / 978-1-4577-1516-7
By: Guoqing Deng; Chunhong Chen;
SET based Boltzmann machine and Hopfield neural networks
2011 / IEEE / 978-1-4577-1516-7
By: Chunhong Chen; Chia-Chin Liu;
A high-speed switch architecture MRS for switched token ring network
1998 / IEEE / 7-80090-827-5
By: An Cai; Debao Xiao; Chunhong Chen;
Provably good algorithm for low power consumption with dual supply voltages
1999 / IEEE / 0-7803-5832-5
By: Chunhong Chen; Sarrafzadeh, M.;
Power reduction by simultaneous voltage scaling and gate sizing
2000 / IEEE / 0-7803-5973-9
By: Chunhong Chen; Sarrafzadeh, M.;
Power optimization of delay constrained circuits
2000 / IEEE / 0-7803-6598-4
By: Nayak, A.; Sarrafzadeh, M.; Chunhong Chen; Banerjee, P.; Haldar, M.;
Potential slack: an effective metric of combinational circuit performance
2000 / IEEE / 0-7803-6445-7
By: Chunhong Chen; Sarrafzadeh, M.; Xiaojian Yang;
Timing driven gate duplication in technology independent phase
2001 / IEEE / 0-7803-6633-6
By: Srivastava, A.; Sarrafzadeh, M.; Chunhong Chen;
Activity-driven clock design
2001 / IEEE
By: Sarrafzadeh, M.; Tellez, G.; Srivastava, A.; Chunhong Chen; Farrahi, A.H.;
On gate level power optimization using dual-supply voltages
2001 / IEEE
By: Chunhong Chen; Sarrafzadeh, M.; Srivastava, A.;
Predicting potential performance for digital circuits
2002 / IEEE
By: Xiaojian Yang; Chunhong Chen; Sarraftadeh, M.;
Probabilistic analysis of rectilinear Steiner trees
2002 / IEEE / 0-7695-1441-3
By: Chunhong Chen;
Power-manageable scheduling technique for control dominated high-level synthesis
2002 / IEEE / 0-7695-1471-5
By: Chunhong Chen; Sarrafzadeh, M.;
Activity-sensitive clock tree construction for low power
2002 / IEEE / 1-5811-3475-4
By: Sarrafzadeh, M.; Changjun Kang; Chunhong Chen;
Simultaneous voltage scaling and gate sizing for low-power design
2002 / IEEE
By: Chunhong Chen; Sarrafzadeh, M.;
Probability-based approach to rectilinear Steiner tree problems
2002 / IEEE
By: Jiang Zhao; Chunhong Chen; Ahmadi, M.;
Timing driven gate duplication
2004 / IEEE
By: Sarrafzadeh, M.; Chunhong Chen; Kastner, R.; Srivastava, A.;
Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems
2004 / IEEE / 1-58113-929-2
By: Hao Min; Chenling Huang; Dawei Jin; Chunhong Chen; Feng Zhou;
Performance of probabilistic approaches to Steiner tree problem
2004 / IEEE / 0-7803-8322-2
By: Chunhong Chen; Jiang Zhao;
Evaluating and Optimizing Power Consumption of Anti-Collision Protocols for Applications in RFID Systems
2004 / IEEE / 1-58113-929-2
By: Hao Min; Chenling Huang; Dawei Jin; Chunhong Chen; Feng Zhou;
A gate duplication technique for timing optimization
2003 / IEEE
By: Chiying Tsui; Chunhong Chen; Ahmadi, M.;
A high-level optimization scheme for low power clock design
2003 / IEEE / 0-7803-8294-3
By: Abdel-Raheem, E.; Chunhong Chen; Changjun Kang;
A low-power CMOS analog multiplier
2006 / IEEE
By: Zheng Li; Chunhong Chen;
Finite state machine implementation with single-electron tunneling technology
2006 / IEEE / 0-7695-2533-4
By: Chunhong Chen; Jialin Mi;
Power-oriented delay budgeting for combinational circuits
2006 / IEEE / 0-7695-2533-4
By: Jialin Mi; Chunhong Chen;
Power-oriented delay budgeting for combinational circuits
2006 / IEEE / 0-7803-9389-9
By: Kwan, H.K.; Chunhong Chen; Jialin Mi;
A novel 12-bit 40-Msample/s low-power low-area pipeline analogue-to-digital converter
2006 / IEEE
By: Esam Abdel-Raheem; Mani Mohajerin; Chunhong Chen;
Performance Evaluation and Optimization of Full Adders with Single-Electron Technology
2006 / IEEE / 1-4244-0038-4
By: Yanjie Mao; Chunhong Chen;
Reliability-Driven Gate Replication for Nanometer-Scale Digital Logic
2007 / IEEE
By: Chunhong Chen;
Quasi-Static Energy Recovery Logic with Single Power-Clock Supply
2007 / IEEE / 1-4244-0920-9
By: Hua Chen; Chunhong Chen; Feng Zhou; Shun Li; Yipin Wu;
A Statistical Reliability Model for Single-Electron Threshold Logic
2008 / IEEE
By: Yanjie Mao; Chunhong Chen;
An experimental study on multi-island structures for single-electron tunneling based threshold logic
2008 / IEEE / 978-1-4244-1683-7
By: Puthucode, V.; Chunhong Chen;
On the behaviors of multi-island structure for single-electron threshold logic circuits
2007 / IEEE / 978-1-4244-0607-4
By: Chunhong Chen; Bharkhada, P.;
Towards reliability improvement for nanoelectronic circuits using gate replication
2007 / IEEE / 978-1-4244-0607-4
By: Feng Zhou; Chunhong Chen;
Design Methodology for Electron-Trap Memory Cells
2008 / IEEE / 978-1-4244-2104-6
By: Chunhong Chen; Bingxi Li;
Modeling Reliability for Single-Electron Tunneling Logic Gates
2008 / IEEE / 978-1-4244-2104-6
By: Chunhong Chen; Yanjie Mao;
Performance analysis and improvement for hybrid CMOS-SET circuit architectures
2008 / IEEE / 978-1-4244-2920-2
By: Guoqing Deng; Chunhong Chen;
Miniaturized dualband loaded frequency selective surfaces with close band spacing
2008 / IEEE / 978-1-4244-2641-6
By: Chunhong Chen; Rongrong Xu; Zhi-yuan Zong; Wen Wu;
Synthesis of symmetrical even-order chebyshev filters
2008 / IEEE / 978-1-4244-2641-6
By: Chunhong Chen; Lan Cui; Jinping Yang; Wen Wu;
A novel dual frequency defected ground structure and its application to filter
2008 / IEEE / 978-1-4244-2641-6
By: Guo Yang; Wen Wu; Chunhong Chen;
Low Power Chien Search for BCH Decoder Using RT-Level Power Management
2011 / IEEE
By: Chunhong Chen; Shu-Yi Wong; Wu, Q.M.J.;
Design of dual-passband cross-coupled filter using stub-loaded open-loop resonators
2009 / IEEE / 978-1-4244-2801-4
By: Chunhong Chen; Jiankang Li; Wen Wu;
Full adder design using hybrid CMOS-SET parallel architectures
2009 / IEEE / 978-981-08-3694-8
By: Guoqing Deng; Chunhong Chen; Guoyan Ren;
An ultra-low power ring oscillator for passive UHF RFID transponders
2010 / IEEE / 978-1-4244-7773-9
By: Chunhong Chen; Guoyan Ren; Farzeen, S.;
Towards robust design of hybrid CMOS-SETs using feedback architectures
2010 / IEEE / 978-1-4244-7032-7
By: Chunhong Chen; Guoqing Deng;
Delay Estimation on Single-Electron Tunneling-Based Logic Gates
2011 / IEEE
By: Chunhong Chen;

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