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Author: Campardo, G.

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A 30M samples/s programmable filter processor
1990 / IEEE
By: Piacentini, P.; Cremonesi, A.; Cavallotti, F.; Nava, F.; Golla, C.; Campardo, G.; Casagrande, G.;
A 40 mm/sup 2/ 3 V 50 MHz 64 Mb 4-level cell NOR-type flash memory
2000 / IEEE / 0-7803-5853-8
By: Kai, Y.; Shimizu, S.; Ohnakado, T.; Sugihara, I.; Bez, R.; Grossi, A.; Modelli, A.; Khouri, P.O.; Torelli, G.; Campardo, G.; Micheloni, R.; Commodaro, S.; Yero, E.; Zammabio, M.; Mognoni, S.; Sacco, A.; Picca, M.; Manstleita, A.; Scotti, M.; Motta, I.; Golla, C.; Pierin, A.; Ohba, A.; Fulatsuya, T.; Makabe, R.; Kawai, S.;
Hierarchical sector biasing organization for flash memories
2000 / IEEE / 0-7695-0689-5
By: Zammattio, M.; Micheloni, R.; Torelli, G.; Khouri, O.; Campardo, G.;
40-mm/sup 2/ 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory
2000 / IEEE
By: Commodaro, S.; Yero, E.; Campardo, G.; Torelli, G.; Khouri, O.; Visconti, A.; Modelli, A.; Grossi, A.; Bez, R.; Pierin, A.; Micheloni, R.; Golla, C.; Motta, I.; Scotti, M.; Manstretta, A.; Picca, M.; Sacco, A.; Mognoni, S.; Zammattio, M.;
Program word-line voltage generator for multilevel flash memories
2000 / IEEE / 0-7803-6542-9
By: Sacco, A.; Micheloni, R.; Khouri, O.; Torelli, G.; Campardo, G.;
Modular architecture for a family of multilevel 256/192/128/64 Mbit 2-bit/cell 3 V-only NOR flash memory devices
2001 / IEEE / 0-7803-7057-0
By: Ragone, G.; Stefanelli, M.; Khouri, O.; Campardo, G.; Fusillo, G.; Silvagni, A.; Crippa, L.; Scotti, M.; Manstretta, A.; Zanardi, S.;
Special issue on flash memory technology
2003 / IEEE
By: Micheloni, R.; Campardo, G.;
An overview of flash architectural developments
2003 / IEEE
By: Scommegna, S.; Scotti, M.; Campardo, G.; Silvagni, A.; Pollara, S.;
The flash memory read path: building blocks and critical aspects
2003 / IEEE
By: Sangalli, M.; Crippa, L.; Micheloni, R.; Campardo, G.;
A 32Mb–4b/cell analog flash memory supporting variable density with 3V–only supply and serial I/O
1999 / IEEE
By: Rocchi, A.; Maurelli, A.; Lhermet, F.; Issartel, C.; Guaitini, G.; De Sandre, G.; Canegallo, R.; Campardo, G.; Pasotti, M.; Rolandi, P.L.; Kramer, A.;
A 0.13-µm CMOS NOR flash memory experimental chip for 4-b/cell digital storage
2002 / IEEE
By: Khouri, O.; Micheloni, R.; Torelli, G.; Fratin, L.; Campardo, G.; Cabrini, A.; Gregori, S.;
1 Gb stacked solution of multilevel NOR flash memory packaged in a LFBGA 8 mm by 10 mm by 1.4 mm of thickness
2006 / IEEE / 1-4244-0275-1
By: Pulici, P.; Dellutri, M.; Campardo, G.; Lo Iacono, F.; Tenerello, A.; Labriola, G.; Di Stefano, R.; Vassallo, F.; Lessio, T.; Vanalli, G.; Stoppino, P.; Guarnaccia, D.;
A Reduced Output Ringing CMOS Buffer
2007 / IEEE
By: Stoppino, P.P.; Pulici, P.; Bartolini, M.; Vanalli, G.P.; Campardo, G.;
Interconnection effects in Package on Package design
2007 / IEEE / 978-1-4244-1223-5
By: Campardo, G.; Candela, G.; Pulici, P.; Lo Iacono, F.; Guarnaccia, D.; Vanalli, G.P.; Dellutri, M.; Lessio, T.; Losavio, A.; Stoppino, P.P.;
Risks for Signal Integrity in System in Package and Possible Remedies
2008 / IEEE / 978-0-7695-3150-2
By: Metra, C.; Angelini, P.; Rossi, D.; Vanalli, G.P.; Campardo, G.;
A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package
2008 / IEEE
By: Vanalli, G.P.; Girardi, A.; Pulici, P.; Campardo, G.; Izzi, R.; Strollo, A.; Ripamonti, G.; Bernardi, G.;
Signal Integrity Flow for System-in-Package and Package-on-Package Devices
2009 / IEEE
By: Pulici, P.; Ripamonti, G.; Campardo, G.; Lo Iacono, F.; Guarnaccia, D.; Dellutri, M.A.; Vanalli, G.P.;
3-D Integration Technologies [Scanning the Issue]
2009 / IEEE
By: Micheloni, R.; Ripamonti, G.; Campardo, G.;
SoC and SiP, the Yin and Yang of the Tao for the New Electronic Era
2009 / IEEE
By: Campardo, G.; Belot, D.; Maurelli, A.;

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