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Author: Atienza, D.

Results

Energy-Efficient Multiobjective Thermal Control for Liquid-Cooled 3-D Stacked Architectures
2011 / IEEE
By: Atienza, D.; Coskun, A.K.; Sabry, M.M.; Brunschwiler, T.; Rosing, T.S.;
Neural Network-Based Thermal Simulation of Integrated Circuits on GPUs
2012 / IEEE
By: Ruggiero, M.; Vincenzi, A.; Sridhar, A.; Atienza, D.;
Modeling and dynamic management of 3D multicore systems with liquid cooling
2009 / IEEE / 978-1-4577-0236-5
By: Coskun, A.K.; Rosing, T.S.; Atienza, D.; Ayala, J.L.;
Fast thermal simulation of 2D/3D integrated circuits exploiting neural networks and GPUs
2011 / IEEE / 978-1-61284-660-6
By: Sridhar, A.; Vincenzi, A.; Atienza, D.; Ruggiero, M.;
3D Thermal-aware floorplanner for many-core single-chip systems
2011 / IEEE / 978-1-4577-1490-0
By: Ayala, J.L.; Risco-Martin, J.L.; Cuesta, D.; Atienza, D.;
A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware
2011 / IEEE / 978-1-4577-1484-9
By: Sciuto, D.; Rana, V.; Clemente, J.A.; Atienza, D.; Beretta, I.;
System-level thermal-aware design of 3D multiprocessors with inter-tier liquid cooling
2011 / IEEE / 978-2-35500-016-4
By: Sabry, M.M.; Sridhar, A.; Atienza, D.;
Structured sparsity models for compressively sensed electrocardiogram signals: A comparative study
2011 / IEEE / 978-1-4577-1470-2
By: Mamaghanian, H.; Vandergheynst, P.; Atienza, D.; Khaled, N.;
A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems
2012 / IEEE / 978-1-4577-2145-8
By: Atienza, D.; Sabry, M.M.; Catthoor, F.;
Tutorial T7A: New Modeling Methodologies for Thermal Analysis of 3D ICs and Advanced Cooling Technologies of the Future
2012 / IEEE / 978-1-4673-0438-2
By: Atienza, D.; Shridhar, A.;
Wearout-aware compiler-directed register assignment for embedded systems
2012 / IEEE / 978-1-4673-1036-9
By: Ahmed, F.; Milor, L.; Atienza, D.; Sabry, M.M.;
Multi-core architecture design for ultra-low-power wearable health monitoring systems
2012 / IEEE / 978-1-4577-2145-8
By: Dogan, A.Y.; Atienza, D.; Burg, A.; Ruggiero, M.; Constantin, J.;
Thermal balancing of liquid-cooled 3D-MPSoCs using channel modulation
2012 / IEEE / 978-1-4577-2145-8
By: Sridhar, A.; Sabry, M.M.; Atienza, D.;
Design exploration of energy-performance trade-offs for wireless sensor networks
2012 / IEEE / 978-1-4503-1199-1
By: Atienza, D.; Rana, V.; Grassi, P.R.; Khaled, N.; Rincon, F.; Beretta, I.;
EigenMaps: Algorithms for optimal thermal maps extraction and sensor placement on multicore processors
2012 / IEEE / 978-1-4503-1199-1
By: Vincenzi, A.; Ranieri, J.; Vetterli, M.; Atienza, D.; Chebira, A.;
Design of ultra-low-power smart wearable systems
2015 / IEEE
By: Murali, S.; Rincon, F.; Surrel, G.; Atienza, D.;
GPU Acceleration for Simulating Massively Parallel Many-Core Platforms
2015 / IEEE
By: Marongiu, A.; Ruggiero, M.; Raghav, S.; Benini, L.; Atienza, D.; Pinto, C.;
3D-ICE: A Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs
2014 / IEEE
By: Brunschwiler, T.; Atienza, D.; Vincenzi, A.; Sridhar, A.;
A Semi-Analytical Thermal Modeling Framework for Liquid-Cooled ICs
2014 / IEEE
By: Atienza, D.; Sabry, M.M.; Sridhar, A.;
Online Energy-Efficient Task-Graph Scheduling for Multicore Platforms
2014 / IEEE
By: Kanoun, K.; van der Schaar, M.; Atienza, D.; Mastronarde, N.;
Automated dynamic memory data type implementation exploration and optimization
2003 / IEEE / 0-7695-1904-0
By: Ykman, C.; Leeman, M.; Deconinck, G.; De Florio, V.; Atienza, D.;
Methodology for refinement and optimization of dynamic memory management for embedded systems in multimedia applications
2003 / IEEE / 0-7803-7795-8
By: Lauwereins, R.; De Florio, V.; Deconinck, G.; Leeman, M.; Atienza, D.; Catthoor, F.; Ykman, C.; Mendias, J.M.;
Dynamic memory management design methodology for reduced memory footprint in multimedia and wireless network applications
2004 / IEEE / 0-7695-2085-5
By: Mamagkakis, S.; Atienza, D.; Soudris, D.; Mendias, J.M.; Catthoor, F.;
Memory-access-aware data structure transformations for embedded software with dynamic data accesses
2004 / IEEE
By: Catthoor, F.; Vandecappelle, A.; Atienza, D.; Daylight, E.G.; Mendias, J.M.;
Garbage collector refinement for new dynamic multimedia applications on embedded systems
2004 / IEEE / 0-7695-2061-8
By: Olcoz, K.; Tirado, F.; Catthoor, F.; Atienza, D.; Velasco, J.M.; Mendias, J.M.;
An integrated hardware/software approach for run-time scratchpad management
2004 / IEEE / 1-51183-828-8
By: Atienza, D.; Marchal, P.; Francesco, P.; Mendias, J.M.; Catthoor, F.; Benini, L.;
Reducing memory accesses with a system-level design methodology in customized dynamic memory management
2004 / IEEE / 0-7803-8631-0
By: Atienza, D.; Soudris, D.; Mendias, J.M.; Catthoor, F.; Mamagkakis, S.;
Custom design of multi-level dynamic memory management subsystem for embedded systems
2004 / IEEE / 0-7803-8504-7
By: Mamagkakis, S.; Mendias, J.M.; Soudris, D.; Catthoor, F.; Poucet, C.; Atienza, D.;
Fast prototyping and refinement of complex dynamic data types in multimedia applications for consumer embedded devices
2004 / IEEE / 0-7803-8603-5
By: Mendias, J.M.; Deconinck, G.; Catthoor, F.; Leeman, M.; Atienza, D.; Lauwereins, R.; De Florio, V.;
A complete network-on-chip emulation framework
2005 / IEEE / 0-7695-2288-2
By: Atienza, D.; Genko, N.; Catthoor, F.; Hermida, R.; Mendias, J.M.; De Micheli, G.;
A novel approach for network on chip emulation
2005 / IEEE / 0-7803-8834-8
By: De Micheli, G.; Atienza, D.; Genko, N.; Catthoor, F.; Hermida, R.; Mendias, J.M.; Benini, L.;
Optimal loop-unrolling mechanisms and architectural extensions for an energy-efficient design of shared register files in MPSoCs
2005 / IEEE / 0-7695-2483-4
By: Atienza, D.; Ayala, J.L.; Lopez-Barrio, C.A.; Hermida, R.; Mendias, J.M.; Lopez-Vallejo, M.;
Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications
2006 / IEEE / 3-9810801-1-4
By: Mamagkakis, S.; Bartzas, A.; Thanailakis, A.; Soudris, D.; Catthoor, F.; Atienza, D.; Pouiklis, G.;
Automated Exploration of Pareto-optimal Configurations in Parameterized Dynamic Memory Allocation for Embedded Systems
2006 / IEEE / 3-9810801-1-4
By: Catthoor, F.; Poucet, C.; Atienza, D.; Mamagkakis, S.; Mendias, J.M.; Soudris, D.;
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
2006 / IEEE / 1-59593-381-6
By: De Micheli, G.; Benini, L.; Poletti, F.; Paci, G.; Del Valle, P.G.; Atienza, D.; Mendias, J.M.;
A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip
2006 / IEEE / 1-59593-381-6
By: Benini, L.; Atienza, D.; Murali, S.; De Micheli, G.;
Systematic design flow for dynamic data management in visual texture decoder of MPEG-4
2006 / IEEE / 0-7803-9389-9
By: Peon, M.; Bartzas, A.; Mendias, M.; Soudris, D.; Catthoort, F.; Atienza, D.; Mamagkakis, S.;
Template-Based Semi-Automatic Profiling of Multimedia Applications
2006 / IEEE / 1-4244-0366-7
By: Poucet, C.; Catthoor, F.; Atienza, D.;
Compilation for Delay Impact Minimization in VLIW Embedded Systems
2006 / IEEE / 0-7695-2689-6
By: Atienza, D.; Ayala, J.L.; Catthoor, F.; Lopez-Vallejo, M.; Raghavan, P.;
A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework
2006 / IEEE / 3-901882-19-7
By: Benini, L.; Mendias, J.M.; Perez, E.A.; Flores, J.G.; De Micheli, G.; Atienza, D.; Del Valle, P.G.; Magan, I.;
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips
2006 / IEEE / 3-901882-19-7
By: Raffo, L.; De Micheli, G.; Benini, L.; Carta, S.; Murali, S.; Angiolini, F.; Meloni, P.; Atienza, D.;
Designing Application-Specific Networks on Chips with Floorplan Information
2006 / IEEE / 1-59593-389-1
By: Raffo, L.; De Micheli, G.; Benini, L.; Carta, S.; Murali, S.; Angiolini, F.; Meloni, P.; Atienza, D.;
Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips
2006 / IEEE / 1-4244-0621-8
By: Pulling, A.; Angiolini, F.; Tamhankar, R.; Murali, S.; De Micheli, G.; Benini, L.; Atienza, D.;
NoC Design and Implementation in 65nm Technology
2007 / IEEE / 0-7695-2773-6
By: Atienza, D.; Meloni, P.; Angiolini, F.; Pullini, A.; Srinivasan Murali; Benini, L.; De Micheli, G.; Raffo, L.;
Improving the Fault Tolerance of Nanometric PLA Designs
2007 / IEEE / 978-3-9810801-2-4
By: Jamaa, M.H.B.; Angiolini, F.; De Micheli, G.; Benini, L.; Atienza, D.;
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors
2007 / IEEE / 1-4244-0920-9
By: Atienza, D.; Ayala, J.L.; Raghavan, P.; Lopez-Vallejo, M.; De Micheli, G.; Catthoor, F.;
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors
2007 / IEEE
By: Raffo, L.; De Micheli, G.; Benini, L.; Carta, S.; Meloni, P.; Atienza, D.; Murali, S.;
Bringing NoCs to 65 nm
2007 / IEEE
By: Angiolini, F.; Pullini, A.; Benini, L.; De Micheli, G.; Atienza, D.; Murali, S.;
Reliability Support for On-Chip Memories Using Networks-on-Chip
2006 / IEEE / 978-0-7803-9706-4
By: Benini, L.; Murali, S.; Atienza, D.; Angiolini, F.; De Micheli, G.;
Feature - NoC emulation: a tool and design flow for MPSoC
2007 / IEEE
By: Atienza, D.; Genko, N.; Benini, L.; De Micheli, G.;
Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems
2007 / IEEE / 0-7695-3077-X
By: Atienza, D.; Apavatjrut, A.; Ayala, J.L.; Lopez-Vallejo, M.;
Reliability-aware design for nanometer-scale devices
2008 / IEEE / 978-1-4244-1921-0
By: Narayanan, V.; DeBole, M.; Del Valle, P.G.; Ayala, J.L.; Benini, L.; De Micheli, G.; Atienza, D.;
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization
2008 / IEEE / 978-3-9810801-3-1
By: De Micheli, G.; Benini, L.; Boyd, S.; Gupta, R.; Atienza, D.; Mutapcic, A.; Murali, S.;
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures
2008 / IEEE / 978-3-9810801-3-1
By: Atienza, D.; Benini, L.; Acquaviva, A.; Carta, S.; De Micheli, G.; Pittau, M.; Mulas, F.; Buttu, M.;
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks
2008 / IEEE / 978-3-9810801-3-1
By: Sanchez-Elez, M.; Qin Zhao; Recas, J.; Paselli, M.; Atienza, D.; De Micheli, G.; Rincon, F.J.; Penders, J.;
System-Level Design for Nano-Electronics
2007 / IEEE / 978-1-4244-1377-5
By: Poli, M.; Bobba, S.K.; Atienza, D.; Benini, L.; De Micheli, G.;
Programmable logic circuits based on ambipolar CNFET
2008 / IEEE / 978-1-60558-115-6
By: Atienza, D.; Ben Jamaa, M.H.; De Micheli, G.; Leblebici, Y.;
Stochastic modeling and analysis for environmentally powered wireless sensor nodes
2008 / IEEE / 978-963-9799-18-9
By: De Micheli, G.; Atienza, D.; Acquaviva, A.; Susu, A.E.;
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories
2008 / IEEE
By: Ben Jamaa, M.H.; De Micheli, G.; Leblebici, Y.; Ionescu, A.M.; Bouvet, D.; Atienza, D.; Moselund, K.E.;
Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization
2008 / IEEE / 978-0-7695-3277-6
By: Hidalgo, J.I.; Atienza, D.; Risco-Martin, J.L.; Lanchares, J.;
Processor Speed Control With Thermal Constraints
2009 / IEEE
By: Boyd, S.; Mutapcic, A.; Gupta, R.; De Micheli, G.; Atienza, D.; Murali, S.;
A control theory approach for thermal balancing of MPSoC
2009 / IEEE / 978-1-4244-2748-2
By: Zanini, F.; De Micheli, G.; Atienza, D.;
A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories
2009 / IEEE / 978-1-4244-2748-2
By: Leblebici, Y.; Atienza, D.; Haykel Ben Jamaa, M.; De Micheli, G.;
Inducing Thermal-Awareness in Multicore Systems Using Networks-on-Chip
2009 / IEEE / 978-1-4244-4408-3
By: Martinez, E.; Atienza, D.;
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
2009 / IEEE / 978-1-4244-3781-8
By: Atienza, D.; Pullini, A.; Jie Zhang; Bobba, S.; De Micheli, G.;
Dynamic thermal management in 3D multicore architectures
2009 / IEEE / 978-1-4244-3781-8
By: Coskun, A.K.; Leblebici, Y.; Rosing, T.S.; Atienza, D.; Ayala, J.L.;
Prediction and management in energy harvested wireless sensor nodes
2009 / IEEE / 978-1-4244-4066-5
By: Piorno, J.R.; Rosing, T.S.; Atienza, D.; Bergonzini, C.;
Wavelet-Based ECG Delineation on a Wearable Embedded Sensor Platform
2009 / IEEE / 978-0-7695-3644-6
By: Boichat, N.; Rincon, F.; Khaled, N.; Atienza, D.;
Thermal-aware data flow analysis
2009 / IEEE / 978-1-6055-8497-3
By: Brisk, P.; Atienza, D.; Ayala, J.L.;
Multicore thermal management with model predictive control
2009 / IEEE / 978-1-4244-3896-9
By: Zanini, F.; De Micheli, G.; Benini, L.; Atienza, D.;
Thermal Balancing Policy for Multiprocessor Stream Computing Platforms
2009 / IEEE
By: Benini, L.; Carta, S.; Acquaviva, A.; Atienza, D.; Mulas, F.; De Micheli, G.;
Run-Time mapping for dynamically-added applications in reconfigurable embedded systems
2009 / IEEE / 978-1-4244-5816-5
By: Sciuto, D.; Santambrogio, M.D.; Atienza, D.; Rana, V.; Beretta, I.;
Multi-lead wavelet-based ECG delineation on a wearable embedded sensor platform
2009 / IEEE / 978-1-4244-7282-6
By: Barbero, V.; Boichat, N.; Rincon, F.; Atienza, D.; Khaled, N.;
Register File Reliability Analysis Through Cycle-Accurate Thermal Emulation
2008 / IEEE / 978-1-4244-6466-1
By: Atienza, D.; Del Valle, P.G.; Ayala, J.L.;
Evaluation and design exploration of solar harvested-energy prediction algorithm
2010 / IEEE / 978-3-9810801-6-2
By: Ali, M.I.; Atienza, D.; Recas, J.; Al-Hashimi, B.M.;
Energy-efficient variable-flow liquid cooling in 3D stacked architectures
2010 / IEEE / 978-3-9810801-6-2
By: Brunschwiler, T.; Rosing, T.S.; Atienza, D.; Coskun, A.K.; Michel, B.;
Temperature sensor placement in thermal management systems for MPSoCs
2010 / IEEE / 978-1-4244-5308-5
By: Jones, C.N.; Atienza, D.; Zanini, F.; De Micheli, G.;
Multicore thermal management using approximate explicit model predictive control
2010 / IEEE / 978-1-4244-5308-5
By: Atienza, D.; Jones, C.N.; Zanini, F.; De Micheli, G.;
Run-time mapping of applications on FPGA-based reconfigurable systems
2010 / IEEE / 978-1-4244-5308-5
By: Rana, V.; Beretta, I.; Sciuto, D.; Atienza, D.;
Scalable instruction set simulator for thousand-core architectures running on GPGPUs
2010 / IEEE / 978-1-4244-6830-0
By: Atienza, D.; Ruggiero, M.; Raghav, S.; Benini, L.; Marongiu, A.; Pinto, C.;
Adaptive Task Migration Policies for Thermal Control in MPSoCs
2010 / IEEE / 978-1-4244-7320-5
By: Hidalgo, J.I.; Ayala, J.L.; Cuesta, D.; Macii, E.; Acquaviva, A.; Atienza, D.;
Thermal-Aware Compilation for Register Window-Based Embedded Processors
2010 / IEEE
By: Sabry, M.M.; Atienza, D.; Ayala, J.L.;
3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling
2010 / IEEE / 978-1-4244-8194-1
By: Atienza, D.; Brunschwiler, T.; Ruggiero, M.; Vincenzi, A.; Sridhar, A.;
Fuzzy control for enforcing energy efficiency in high-performance 3D systems
2010 / IEEE / 978-1-4244-8194-1
By: Sabry, M.M.; Atienza, D.; Coskun, A.K.;
Island-Based Adaptable Embedded System Design
2011 / IEEE
By: Beretta, I.; Rana, V.; Atienza, D.; Sciuto, D.;
Run-time adaptable on-chip thermal triggers
2011 / IEEE / 978-1-4244-7516-2
By: Atienza, D.; Kumar, P.;
Temperature-aware processor frequency assignment for MPSoCs using convex optimization
2007 / IEEE / 978-1-5959-3824-4
By: Mutapcic, A.; Murali, S.; De Micheli, G.; Boyd, S.; Gupta, R.; Atienza, D.;
A real-time compressed sensing-based personal electrocardiogram monitoring system
2011 / IEEE / 978-3-9810801-8-6
By: Kanoun, K.; Atienza, D.; Khaled, N.; Mamaghanian, H.;
A high-performance parallel implementation of the Chambolle algorithm
2011 / IEEE / 978-3-9810801-8-6
By: Nacci, A.A.; Beretta, I.; Akin, A.; Atienza, D.; Santambrogio, M.D.; Rana, V.;
Attaining Single-Chip, High-Performance Computing through 3D Systems with Active Cooling
2011 / IEEE
By: Sabry, M.M.; Atienza, D.; Jie Meng; Coskun, A.;
Hierarchical Thermal Management Policy for High-Performance 3D Systems With Liquid Cooling
2011 / IEEE
By: De Micheli, G.; Atienza, D.; Sabry, M.M.; Zanini, F.;
Real-time compressed sensing-based electrocardiogram compression on energy-constrained wireless body sensors
2011 / IEEE / 978-1-4244-9474-3
By: Atienza, D.; Khaled, N.; Mamaghanian, H.; Vandergheynst, P.;
Thermal analysis and active cooling management for 3D MPSoCs
2011 / IEEE / 978-1-4244-9474-3
By: Coskun, A.K.; Atienza, D.; Sabry, M.M.;
Thermal-aware system-level modeling and management for Multi-Processor Systems-on-Chip
2011 / IEEE / 978-1-4244-9474-3
By: Benini, L.; Atienza, D.; Zanini, F.; De Micheli, G.;
GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms
2011 / IEEE / 978-1-4577-0129-0
By: Atienza, D.; Ruggiero, M.; Marongiu, A.; Raghav, S.; Pinto, C.; Benini, L.;
A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design
2011 / IEEE
By: Sciuto, D.; Atienza, D.; Rana, V.; Beretta, I.;

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