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Topic: Output Buffers

Results

A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS
2011 / IEEE
By: Shen-Iuan Liu; Bo-Yu Lin;
SPAD Smart Pixel for Time-of-Flight and Time-Correlated Single-Photon Counting Measurements
2012 / IEEE
By: Paschen, U.; Weyers, S.; Durini, D.; Tisa, S.; Zappa, F.; Brockherde, W.; Tosi, A.; Bronzi, D.; Bellisai, S.; Markovic, B.; Villa, F.;
High-speed column-line driving with polarity switch-embedded output buffer amplifiers for TFT-LCD application
2015 / IEEE
By: Kim, H.; Ko, J.; An, C.; Kong, B.;
A new self-routing switch driven with input-to-output address difference
1988 / IEEE
By: Imagawa, H.; Hagishima, K.; Urushidani, S.;
A 10-b 15-MHz CMOS recycling two-step A/D converter
1990 / IEEE
By: Song, B.-S.; Tompsett, M.F.; Lee, S.-H.;
High-speed signal switching with a monolithic integrated p-i-n/amp/switch on indium phosphide
1991 / IEEE
By: Deblis, D.; Eng, J.; Yee, C.M.L.; Kim, S.J.; Davisson, P.S.; Jeong, J.; Vella-Coleiro, G.P.; Bylsma, R.B.; Seabury, C.W.; Jhee, Y.K.;
Markov-modulated flow model for the output queues of a packet switch
1990 / IEEE / 0-8186-2049-8
By: Guerin, R.; Chen, J.S.-C.; Stern, T.E.;
A 250 Mb/s 32*32 CMOS crosspoint LSI for ATM switching systems
1990 / IEEE
By: Maeda, T.; Ouchi, M.; Yoshida, S.; Saito, T.; Sakamoto, T.; Karube, S.; Akata, M.;
A video delay line compiler
1990 / IEEE
By: Senn, P.; Joanblanq, C.; Rothan, F.;
Analysis, control and design of crossbar and banyan based broadband packet switches, for integrated traffic
1990 / IEEE
By: Shaikh, S.Z.; Szymanski, T.H.; Schwartz, M.;
An integrated GPS receiver with synthesizer and downconversion functions
1991 / IEEE / 0-87942-591-1
By: Pulver, J.R.; Mason, C.H.; Chao, A.; Herman, R.M.;
Analysis of a packet switch with input and output buffers and speed constraints
1991 / IEEE / 0-87942-694-2
By: Gupta, A.K.; Georganas, N.D.;
Performance analysis of nonblocking packet switch with input and output buffers
1992 / IEEE
By: Kubota, K.; Murata, M.; Oie, Y.; Miyahara, H.;
Throughput and packet loss in deflection routing multichannel-metropolitan area networks
1991 / IEEE / 0-87942-697-7
By: Zanolini, G.; Trecordi, V.; Decina, M.;
Effect of contention resolution rules on the performance of deflection routing
1991 / IEEE / 0-87942-697-7
By: Li, V.O.K.; Choudhury, A.K.;
On the performance of an ATM switch with multichannel transmission groups
1993 / IEEE
By: Lin, A.Y.-M.; Silvester, J.A.;
Performance analysis of deflection routing multichannel-metropolitan area networks
1992 / IEEE / 0-7803-0602-3
By: Decina, M.; Zanolini, G.; Trecordi, V.;
A poly-Si defect-tolerant scanner for large area AMLCDs
1993 / IEEE / 0-7803-0987-1
By: Hayama, H.; Asada, H.; Okumura, F.; Sera, K.; Saito, T.;
13 Gb/s Si-bipolar AGC amplifier IC with high gain and wide dynamic range for optical-fiber receivers
1994 / IEEE
By: Rein, H.-M.; Moller, M.; Wernz, H.;
Performance evaluation of a source service node architecture under random traffic
1993 / IEEE / 0-7803-0917-0
By: Mouftah, H.T.; Fai Fan;
A Si-bipolar AGC amplifier IC with high gain and wide dynamic range for 10 Gb/s optical-fiber receivers
1994 / IEEE / 0-7803-1418-2
By: Rein, H.-M.; Moller, M.; Wernz, H.;
Performance analysis of output buffered multipath multistage interconnection networks
1993 / IEEE / 0-7803-0950-2
By: Mouftah, H.; Elmahgiubi, O.;
Performance analysis of an ATM Clos switch under symmetric "bursty geometric" traffic
1994 / IEEE / 0-7803-9992-7
By: Beylot, A.-L.; Kohlenberg, I.; Becker, M.;
An output queueing batcher-banyan ATM switch architecture
1993 / IEEE / 0-7803-0953-7
By: Kim, H.; Collier, B.;
Performance analysis of multipath multistage interconnection networks with nonuniform output traffic distribution
1996 / IEEE / 0-8186-7376-1
By: Jungwan Cho; Seungryul Maeng; Hyunsoo Yoon; Boseob Kwon; Byungho Kim;
A new shift-register based ATM switch
1996 / IEEE / 0-8186-7585-3
By: Sabaa, A.; El Guibaly, F.; Shpak, D.;
Performance evaluation of Clos networks under bursty traffic
1996 / IEEE / 0-8186-7460-1
By: Da-Chiang Chang; De-Ron Liang;
Evaluating performance of the MPQ policy for input and output queueing ATM switch supporting multiple traffic classes
1995 / IEEE / 0-7803-2579-6
By: Ahmed, S.;
Performance analysis of output buffers in multistage interconnection networks with multiple paths
1995 / IEEE / 0-81867195-5
By: Kim, B.; Kwon, B.; Cho, J.; Yoon, H.; Park, J.;
Clos-Knockout: a large-scale modular multicast ATM switch
1996 / IEEE / 0-7803-3336-5
By: Chan, K.S.; Chan, S.; Yeung, K.L.; Ko, K.T.; Wong, E.W.M.;
Design of a generalized priority queue manager for ATM switches
1997 / IEEE
By: Chao, H.J.; Jeong, D.; Jenq, Y.-R.; Cheng, H.;
Performance aspects of switched SCI systems
1997 / IEEE / 0-8186-8117-9
By: Liebhart, M.;
Second order /spl Delta//spl Sigma/ modulators using AlGaAs/GaAs HBTS
1994 / IEEE / 0-7803-1975-3
By: Keh-Chung Wang; Pierson, R.; Nubling, R.; Beccue, S.; Nary, K.R.; Jayaraman, A.; Zampardi, P.;
New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area
1997 / IEEE / 0-7803-3985-1
By: Tung-Yang Chen; Ming-Dou Ker; Chung-Yu Wu;
Shared concentration output queueing switch with middle buffer at input of Batcher-banyan network
1997 / IEEE / 0-7803-4198-8
By: Sasase, I.; Shiokawa, S.; Nishino, Y.;
Teletraffic engineering in a broad-band era
1997 / IEEE
By: Laevens, K.; Michiel, H.;
Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's
1998 / IEEE
By: Watanabe, S.; Oowaki, Y.; Takashima, D.; Ohuchi, K.;
Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology
1998 / IEEE
By: Ming-Dou Ker;
Guaranteeing real-time traffic through an ATM network
1997 / IEEE / 0-8186-7743-0
By: Tindell, K.; Sjodin, M.; Hansson, H.;
Multipriority packet switching on the HYPER switch
1998 / IEEE / 0-7803-4874-5
By: Mabo Ito; Yue He; Alnuweiri, H.M.;
Connection admission control for indoor multimedia wireless communications
1998 / IEEE / 0-7803-4320-4
By: Zhuang, W.; Chak, J.Q.-J.;
Tandem-crosspoint ATM switch with input and output buffers
1998 / IEEE
By: Yamanaka, N.; Oki, E.;
Simulation and modeling of a multicast ATM switch
1999 / IEEE / 0-7695-0013-7
By: Balakrishnan, M.; Siddabathuni, A.C.;
Performance analysis of knockout packet switch with batcher network for multiple classes
1998 / IEEE / 0-7803-4984-9
By: Sasase, I.; Nishino, Y.;
Accurate modeling of simultaneous switching noise in low voltage digital VLSI
1999 / IEEE / 0-7803-5471-0
By: Gyu Moon; Ismail, M.; Sang Won Song; Dong Yong Kim;
High-radix CORDIC for vector rotation with pipelined FPGA implementation
1999 / IEEE / 0-7803-5682-9
By: Kantabutra, V.;
Overflow probability in shared cell switched buffers
2000 / IEEE
By: Schormans, J.A.; Pitts, J.M.;
Performance of route-information based prioritization (RIBP) for ATM networks
2000 / IEEE / 0-7803-6394-9
By: Yamaguchi, T.; Miki, T.; Sugawara, S.;
2-GHz RF front-end circuits in CMOS/SIMOX operating at an extremely low voltage of 0.5 V
2000 / IEEE
By: Yamagishi, A.; Kodate, J.; Tsukahara, T.; Harada, M.; Yamada, J.;
A fast round robin priority port scheduler for high capacity ATM switches
2001 / IEEE / 0-7803-7093-7
By: Shahrier, S.M.;
A shared knockout ATM switch for reduction of hardware under variable hot-spot traffic
2001 / IEEE / 0-7803-7097-1
By: Nishino, Y.; Sasase, I.;
A programmable filter with self-tuning for DMT VDSL receiver
2002 / IEEE / 0-7803-7363-4
By: Chorng-Kuang Wang; Chien-Chih Lin; Chia-Hua Chou;
An optimized structure CMOS dual-modulus prescaler using dynamic circuit technique
2002 / IEEE / 0-7803-7490-8
By: Bingxue Shi; Baoyong Chi;
A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique
2003 / IEEE
By: Seong-Jun Song; Sung Min Park; Hoi-Jun Yoo;
An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology
2004 / IEEE
By: Salama, C.A.T.; Vessal, F.;
A 24.9-GHz emitter-degenerated SiGe bipolar VCO
2003 / IEEE / 0-7803-7800-8
By: Kornegay, K.T.; Duster, J.S.; Zhan, J.-H.C.;
A 43Gb/s 2:1 selector IC in 90nm CMOS technology
2004 / IEEE / 0-7803-8267-6
By: Horinaka, M.; Yamamoto, T.; Onodera, H.; Hashimoto, K.; Nomura, H.; Yamazaki, D.;
A 35.2-37.6 GHz LC VCO in a 70/100 GHz f/sub T//f/sub max/ SiGe technology
2004 / IEEE / 0-7803-8267-6
By: Veenstra, H.; van der Heijden, E.;
60 GHz VCO with wideband tuning range fabricated on VLSI SOI CMOS technology
2004 / IEEE / 0-7803-8331-1
By: Jackel, H.; Buren, G.; Morf, T.; Ellinger, F.; Kromer, C.; Schmatz, M.; Rodoni, L.; Sialm, G.;
Characteristics of single-event upsets in a fabric switch (AD8151)
2004 / IEEE
By: LaBel, K.A.; Marshall, P.W.; Hak Kim; McMorrow, D.; Carts, M.A.; Buchner, S.;
A 25-GHz emitter degenerated LC VCO
2004 / IEEE
By: Kornegay, K.T.; Duster, J.S.; Jing-Hong Conan Zhan;
Packet switch architecture with multiple output queueing
2004 / IEEE / 0-7803-8794-5
By: Glabowski, M.; Danilewicz, G.; Kleban, J.; Kabacinski, W.;
A CMOS sensor array IC for Van der Waals enhanced MOSFET and Taguchi type sensors
2004 / IEEE / 0-7803-8692-2
By: Kish, L.; Sonkusale, S.R.; Agarwal, A.; Kim, Y.; Marlow, W.; Cheng, M.;
Automated nonlinear macromodelling of output buffers for high-speed digital applications
2005 / IEEE / 1-59593-058-2
By: Ning Dong; Roychowdhury, J.;
A QoS provisioned CIOQ packet switch using crossbar structure with m internal links
2005 / IEEE / 0-7695-2422-2
By: Motoyama, S.; Roberto dos Santos, C.;
Full-rate injection-locked 10.3Gb/s clock and data recovery circuit in a 45GHz-f/sub T/ SiGe process
2005 / IEEE / 0-7803-9023-7
By: Duster, J.S.; Zhan, J.-H.C.; Kornegay, K.T.;
Backplane equalization comparison for 10-Gb/s data communication with 0.25-�m SiGe BiCMOS and 0.18-�m CMOS feed-forward equalizers
2007 / IEEE / 978-2-87487-002-6
By: Kim, H.S.; Laskar, J.; Gebara, E.; Raghavan, A.;
An Integrated 60-GHz Front-end Receiver with a Frequency Tripler Using 0.13-�m CMOS Technology
2007 / IEEE / 978-1-4244-1377-5
By: Po-Hung Chen; Chung-Yu Wu; Min-Chiao Chen;
1V supply CMOS DEMUX for 40-GB/S optical communication systems
2008 / IEEE / 978-1-4244-1945-6
By: Kwasniewski, T.; Bangli Liang; Dezhong Cheng; Bo Wang; Dianyong Chen;
A Sub-1V 22-GHz CMOS Injection-Locked Frequency Divider
2008 / IEEE / 978-2-87487-007-1
By: Tzuang, C.-K.C.; Chih-Chia Chen;
A W-Band Highly Linear SiGe BiCMOS Double-Balanced Active Up-Conversion Mixer Using Multi-Tanh Triplet Technique
2010 / IEEE
By: Chen, A.Y.-K.; Jenshan Lin; Young-Kai Chen; Baeyens, Y.;
Behavioral Modeling of IC Memories From Measured Data
2011 / IEEE
By: Teixeira, H.M.; Pedro, J.C.; Canavero, F.G.; Cunha, T.R.; Girardi, A.; Rigazio, L.; Stievano, I.S.; Vitale, F.; Izzi, R.;

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