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Topic: Mos Memory Circuits

Results

Estimation of Trapped Charge Density in SONOS Flash Memory Using a Parallel Capacitor Model
2011 / IEEE
By: Hua-Min Li; Won Jong Yoo; Gang Zhang;
Accurate Compact Modeling for Sub-20-nm nand Flash Cell Array Simulation Using the PSP Model
2012 / IEEE
By: Kihwan Choi; Jongwook Jeon; Wookghee Hahn; Myounggon Kang; Il Han Park; Sunghee Yun; Chilhee Chung; Young-Kwan Park; Keun-Ho Lee; Gi-Young Yang;
A SPICE Compact Model of Metal Oxide Resistive Switching Memory With Variations
2012 / IEEE
By: Ximeng Guan; Wong, H.-S.P.; Shimeng Yu;
The test methods for some failure modes of 1K MOS RAM
1974 / IEEE
By: Kodama, K.; Kasai, Y.;
3D Simulation of charge collection and MNU in SEU hardened storage cells
2009 / IEEE / 978-1-4577-0493-2
By: Yuanfu Zhao; Lin Liu; Suge Yue;
Study on nanoparticles embedded multilayer gate dielectric MOS non volatile memory devices
2011 / IEEE / 978-1-4577-0378-2
By: Sarkar, C.K.; Sengupta, A.;
Plasma damage failure analysis cases study by EBIC detection on nano-probing SEM system
2011 / IEEE / 978-1-4577-0158-0
By: Wen Pin Lin; Tseng, C.E.; Yi Heang Chen;
Fabrication and modeling of Ag/TiO2/ITO memristor
2011 / IEEE / 978-1-61284-857-0
By: Sangjin Lee; Kyoungrok Cho; Kavehei, O.; Eshraghian, K.; Abbott, D.; Al-Sarawi, S.; Sung-Jin Kim;
First principle study of the stability of H atoms in SiN layers on MONOS-type memories during program/erase operations
2011 / IEEE / 978-1-61284-418-3
By: Yamaguchi, K.; Shigeta, Y.; Shiraishi, K.; Kamiya, K.; Otake, A.;
Low power memristor-based ReRAM design with Error Correcting Code
2012 / IEEE / 978-1-4673-0772-7
By: Dimin Niu; Yuan Xie; Yang Xiao;
Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM
2012 / IEEE / 978-1-4673-0908-0
By: Matsunaga, S.; Hanyu, T.;
Optimizing state-of-the-art 28nm core/SRAM device performance by cryo-implantation technology
2012 / IEEE / 978-1-4577-2084-0
By: Chen, I.C.; Colombeau, B.; Gossmann, H.-J.; Lu, S.; Guo, B.N.; Cheng, O.; Cheng, Y.C.; Wu, J.Y.; Chan, M.; Huang, C.T.; Hsu, B.C.; Wang, H.Y.; Lu, T.Y.; Fu, C.; Huang, Y.S.; Tsai, C.H.; Chen, W.J.; Lin, G.P.; Li, C.I.; Yang, C.L.;
NeoSilicon based nanoelectromechanical information devices
2012 / IEEE / 978-1-4673-0238-8
By: Oda, S.;
Algorithm-Enhanced Retention Based on Megabit Array of $\hbox{Cu}_{x}\hbox{Si}_{y}\hbox{O}$ RRAM
2012 / IEEE
By: Qin-Tian Zou; Huang, R.; Yin-Yin Lin; Ling-Ming Yang; Ya-Li Song; Yan-Liang Wang; Jin-Gang Wu;
Dependence of charge storage and programming characteristics on dot number of floating dot memory
2008 / American Institute of Physics
By: Anri Nakajima; Tomo Fujiaki; Yuusuke Fukuda;
A new technique for measuring coupling coefficients and 3-D capacitance characterization of floating-gate devices
1994 / IEEE
By: Choi, W.L.; Kim, D.M.;
Simulation tool for design and management optimization of automated interbay material handling and storage systems for large wafer fab
1995 / IEEE
By: Pelagagge, P.M.; Cardarelli, E.;
Effects of erase source bias on Flash EPROM device reliability
1995 / IEEE
By: San, K.T.; Ma, T.P.; Kaya, C.;
Hardware implementation of ART1 memories using a mixed analog/digital approach
1994 / IEEE / 0-7803-1901-X
By: Liou, J.J.; Ho, C.S.; Georgiopoulos, M.;
Investigation of the soft-write mechanism in source-side injection flash EEPROM devices
1995 / IEEE
By: Wellekens, D.; Van Houdt, J.F.; Maes, H.E.; Groeseneken, G.;
Self-Aligned LOCOS/Trench (SALOT) combination isolation technology planarized by chemical mechanical polishing
1994 / IEEE / 0-7803-2111-1
By: Ahn, S.T.; Kim, J.D.; Hong, C.G.; Ko, J.H.; Ahn, S.J.; Park, T.; Lee, M.Y.;
A highly practical modified LOCOS isolation technology for the 256 Mbit DRAM
1994 / IEEE / 0-7803-2111-1
By: Hwang, C.G.; Ahn, S.J.; Ahn, D.H.; Lee, M.Y.; Griffin, P.B.; Ahn, S.T.; Lee, W.S.; Hwang, M.W.;
1G DRAM cell with diagonal bit-line (DBL) configuration and edge operation MOS (EOS) FET
1994 / IEEE / 0-7803-2111-1
By: Mori, H.; Shibahara, K.; Koyama, K.; Hamada, T.; Watanabe, H.; Oikawa, R.; Ohnishi, S.; Itoh, K.; Yamashita, H.; Kojima, Y.; Nakajima, K.; Kamiyama, S.;
An EEPROM model for low power circuit design and simulation
1994 / IEEE / 0-7803-2111-1
By: Kuo-Tung Chang; Cavins, C.; Higman, J.; Tat-Kwan Yu; Orlowski, M.;
A 0.67 /spl mu/m/sup 2/ self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROMs
1994 / IEEE / 0-7803-2111-1
By: Shirota, R.; Hemink, G.J.; Watanabe, H.; Shuto, S.; Watanabe, S.; Maruyama, T.; Satoh, S.; Aritome, S.; Masuoka, F.;
Experimental characterization of circuits for controlled programming of floating-gate MOSFET's
1995 / IEEE
By: Lanzoni, M.; Ricco, B.;
High-speed circuit design with scaled-down MOSFETs and low supply voltage
1993 / IEEE / 0-7803-1281-3
By: Sakurai, T.;
High-endurance ultra-thin tunnel oxide in MONOS device structure for dynamic memory application
1995 / IEEE
By: Wann, H.C.; Chenming Hu;
Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices
1996 / IEEE
By: Mori, S.; Sakagami, E.; Arai, N.; Yoshikawa, K.; Kamiya, E.; Tsunoda, H.; Meguro, H.; Sato, M.; Araki, Y.Y.;
A new analytical model of SRAM cell stability in low-voltage operation
1996 / IEEE
By: Ichikawa, T.; Sasaki, M.;
Latent gate oxide defects caused by CDM-ESD
1995 / IEEE / 1-878303-59-7
By: Reiner, J.C.;
The effect of the floating gate/tunnel SiO/sub 2/ interface on FLASH memory data retention reliability
1996 / IEEE / 0-7803-2753-5
By: Kubota, T.; Muramatsu, S.; Ando, K.;
Limitations on oxide thicknesses in flash EEPROM applications
1996 / IEEE / 0-7803-2753-5
By: Gladstone, S.M., IV; Runnion, E.F.; Mitros, J.; Lie, L.; Dumin, D.J.; Scott, R.S.;
Non-uniform current flow through thin oxide after Fowler-Nordheim current stress
1996 / IEEE / 0-7803-2753-5
By: Yamada, S.; Hashimoto, K.; Hazama, H.; Yamane, T.; Amemiya, K.;
Excess currents induced by hot-hole injection and F-N stress in thin SiO/sub 2/ films [flash memories]
1996 / IEEE / 0-7803-2753-5
By: Teramoto, A.; Yasuoka, A.; Hirayama, M.; Matsui, Y.; Kobayashi, K.;
Trapped hole enhanced stress induced leakage currents in NAND EEPROM tunnel oxides
1996 / IEEE / 0-7803-2753-5
By: Shimizu, K.; Hemink, G.J.; Shirota, R.; Aritome, S.;
A low power 77 K nano-memory with single electron nano-crystal storage
1995 / IEEE / 0-7803-2788-8
By: Tiwari, S.; Hanafi, H.; Chan, K.; Wei Chen; Rana, F.;
A novel Si/SiGe sandwich polysilicon TFT for SRAM applications
1995 / IEEE / 0-7803-2788-8
By: Le-Tien Jung; Manna, I.; Banerjee, S.;
High field stress induced leakage current in 3.0-nm NO-grown gate dielectric films
1995 / IEEE / 0-7803-2624-5
By: Ze-Qiang Yao; Yeow, Y.T.; Dimitrijev, S.; Harrison, H.B.;
An EPROM cell with a magnesium electronic injector
1995 / IEEE / 0-7803-2624-5
By: Sik On Kong; Sai Peng Wong; Chee Yee Kwok;
Characterization of split-gate flash memory devices: reliability, gate-disturbance and capacitive coupling coefficients
1995 / IEEE / 0-7803-2624-5
By: Jun, Y.; Kim, D.M.; Choi, I.; Kim, J.W.; Sohn, Y.S.;
The numerical simulation of substrate and gate currents in MOS and EPROMs
1995 / IEEE / 0-7803-2700-4
By: Piccinini, F.; Concannon, A.; Lombardi, C.; Mathewson, A.;
Short channel enhanced degradation during discharge of flash EEPROM memory cell
1995 / IEEE / 0-7803-2700-4
By: Shengwen Luan; Hsu, J.; Jian Chen; Jih Lien; Yuan Tang; Longcor, S.; Chi Chang; Haddad, S.; Liu, D.;
A 0.54 /spl mu/m/sup 2/ self-aligned, HSG floating gate cell (SAHF cell) for 256 Mbit flash memories
1995 / IEEE / 0-7803-2700-4
By: Shirai, H.; Okazawa, T.; Ono, H.; Watanabe, H.; Honma, I.; Kubota, T.;
A scalable low power vertical memory
1995 / IEEE / 0-7803-2700-4
By: Hanafi, H.I.; Matsushita, K.; Garg, N.; Thomas, A.; Kocon, W.; Burns, S.; Tiwari, S.;
0.228 /spl mu/m/sup 2/ trench cell technologies with bottle-shaped capacitor for 1 Gbit DRAMs
1995 / IEEE / 0-7803-2700-4
By: Nakasugi, T.; Shibata, T.; Takashima, D.; Hamamoto, T.; Niiyama, H.; Shino, T.; Ishibashi, Y.; Aoki, H.; Habu, M.; Noauchi, M.; Ozaki, T.; Sugihara, K.; Yamaguchi, H.; Sato, S.; Magoshi, T.; Hattori, K.; Nishimura, E.; Kato, Y.;
High endurance ultra-thin tunnel oxide for dynamic memory application
1995 / IEEE / 0-7803-2700-4
By: Chenming Hu; Wann, C.H.-J.;
Giga-bit DRAM cells with low capacitance and low resistance bit-lines on buried MOSFETs and capacitors by using bonded SOI technology-reversed stacked capacitor (RSTC) cell
1995 / IEEE / 0-7803-2700-4
By: Fukano, T.; Nara, Y.; Asano, K.; Horie, H.; Nakamura, S.; Sasaki, N.;
Using n-channel TFTs without LDD structures for high stabilities of 1.2-V high-density SRAMs
1995 / IEEE / 0-7803-2700-4
By: Gong, H.I.; Lee, K.H.; Diodato, P.W.; Liu, C.T.;
A double-level-V/sub th/ select gate array architecture for multilevel NAND flash memories
1996 / IEEE
By: Tanaka, T.; Takeuchi, K.; Nakamura, H.;
A long data retention SOI-DRAM with the body refresh function
1996 / IEEE / 0-7803-3339-X
By: Tsukude, M.; Morishita, F.; Tomishima, S.; Arimoto, K.; Yamagata, T.;
Non-volatile FCG (ferroelectric-capacitor and transistor-gate connection) memory cell with non-destructive read-out operation
1996 / IEEE / 0-7803-3342-X
By: Fujieda, S.; Katoh, Y.; Kunio, T.; Hayashi, Y.;
Data retention times in SOI-DRAMs
1996 / IEEE / 0-7803-3342-X
By: Jong-Woo Park; Ki-Nam Kim; Jae-Kwan Park; Seung-Kuk Lee; Sang-Hoon Lee; Dong-Uk Choi; Hyoung-Sub Kim;
Design and performance of SOI pass transistors for 1 Gbit DRAMs
1996 / IEEE / 0-7803-3342-X
By: Houston, T.W.; Teng, C.W.; Yin Hu; Aton, T.J.; Joyner, K.;
Dynamic data retention and implied design criteria for floating-body SOI DRAM
1996 / IEEE
By: Dongwook Suh; Pelella, M.M.; Fossum, J.G.;
Characterization and simulation of hot carrier effect on erasing gate current in flash EEPROMs
1995 / IEEE / 0-7803-2031-X
By: Chen, T.; Tahui Wang; Chimoon Huang; Shone, F.C.; Chang, A.; Peng, N.C.;
Reliability evaluation of thin gate oxide using a flat capacitor test structure
1995 / IEEE / 0-7803-2065-4
By: Mitsuhashi, J.; Katsumata, M.; Koyama, H.; Mashiko, Y.; Kobayashi, K.;
Precise measurement of P-N junction leakage current generated in Si subsurface
1995 / IEEE / 0-7803-2065-4
By: Mizutani, T.; Horikawa, M.; Kitano, T.; Noda, K.;
A new technique for measuring threshold voltage distribution in flash EEPROM devices
1995 / IEEE / 0-7803-2065-4
By: Himeno, T.; Miyamoto, J.; Itoh, Y.; Kanda, K.; Masuda, K.; Oshikiri, M.; Sakui, K.; Hazama, H.; Matsukawa, N.;
A high performance SI memory cell
1994 / IEEE / 0-7803-2428-5
By: Persoon, G.G.; Leeuwenburgh, A.J.; Leenaerts, D.M.W.;
Driving source-line (DSL) cell architecture for sub-1-V high-speed low-power applications
1995 / IEEE / 0-7800-2599-0
By: Nagano, T.; Mizuno, H.;
A 250 mV bit-line swing scheme for a 1 V 4 Gb DRAM
1995 / IEEE / 0-7800-2599-0
By: Takashima, D.; Inaba, T.; Ohuchi, K.; Watanabe, S.; Ozaki, T.; Oowaki, Y.;
/spl alpha/-particle-induced soft errors in submicron SOI SRAM
1995 / IEEE / 0-7803-2602-4
By: Sugii, T.; Suzuki, K.; Tosaka, Y.;
Analysis and current-mode implementation of asymptotically stable exponential bidirectional associative memory
1995 / IEEE / 0-7803-2570-2
By: Jeng-Ming Wu; Chua-Chin Wang;
Diagonal MOSFETs characterization for 256M DRAM and beyond
1995 / IEEE / 0-7803-2773-X
By: Jiann Liu; Richardson, W.F.; Coleman, D.J., Jr.; Teng, C.W.; Yin Hu; Aur, S.; Chi-Chien Ho;
Write/verify free analog non-volatile memory using a neuron-MOS comparator
1996 / IEEE / 0-7803-3073-0
By: Shibata, T.; Yamashita, Y.; Ohmi, T.;
The fabrication and characterization of EEPROM arrays on glass using a low-temperature poly-Si TFT process
1996 / IEEE
By: Young, N.D.; French, I.D.; McCulloch, D.J.; Bunn, R.M.; Harkin, G.;
Floating-body concerns for SOI dynamic random access memory (DRAM)
1996 / IEEE / 0-7803-3315-2
By: Mandelman, J.A.; Hanafi, H.I.; Gautier, J.; Kalter, H.L.; Dennard, R.H.; DeBrosse, J.K.; Barth, J.E.;
Analysis of floating-body-induced leakage current in 0.15 /spl mu/m SOI DRAM
1996 / IEEE / 0-7803-3315-2
By: Yoshimi, M.; Terauchi, M.;
To suppress UV damage on the subthreshold characteristic of TFT during hydrogenation for high density TFT SRAM
1997 / IEEE
By: Liang, M.S.; Hwang, K.C.; Chen, C.W.; Fang, Y.K.; Lee, K.Y.; Wuu, S.G.;
A shallow-trench-isolation flash memory technology with a source-bias programming method
1996 / IEEE / 0-7803-3393-4
By: Kato, M.; Tanaka, T.; Adachi, T.;
Novel self-limiting program scheme utilizing N-channel select transistors in P-channel DINOR flash memory
1996 / IEEE / 0-7803-3393-4
By: Takada, H.; Ohnakado, T.; Abe, H.; Satoh, S.; Sugahara, K.; Hayashi, K.;
A 0.23 /spl mu/m/sup 2/ double self-aligned contact cell for gigabit DRAMs with a Ge-added vertical epitaxial Si pad
1996 / IEEE / 0-7803-3393-4
By: Yamaguchi, H.; Nakajima, K.; Iwao, S.; Saino, K.; Mori, H.; Tatsumi, T.; Hada, H.; Kasai, N.; Koga, H.; Koyama, K.; Takemura, K.; Kato, Y.; Ando, K.; Hashimoto, T.; Nishizawa, A.; Yoshida, K.; Hirasawa, S.; Tokunaga, K.; Yamada, Y.;
Simultaneously formed storage node contact and metal contact cell (SSMC) for 1 Gb DRAM and beyond
1996 / IEEE / 0-7803-3393-4
By: Lee, J.G.; Park, J.W.; Kim, D.H.; Kim, J.S.; Lee, J.Y.; Shin, Y.C.; Kim, K.N.; Lee, K.H.;
Si single-electron MOS memory with nanoscale floating-gate and narrow channel
1996 / IEEE / 0-7803-3393-4
By: Chou, S.Y.; Leobandung, E.; Langjie Guo;
Limitations and challenges of multigigabit DRAM chip design
1997 / IEEE
By: Itoh, K.; Watanabe, T.; Kimura, S.; Nakagome, Y.;
2-transistor-cell 4-valued universal-literal CAM for a cellular logic image processor
1997 / IEEE / 0-7803-3721-2
By: Hanyu, T.; Kameyama, M.; Arakaki, M.;
Low dose ion implantation characterization for Vt control
1996 / IEEE / 0-7803-3289-X
By: Bala, K.; Short, A.; Glawischnig, H.;
Improvement of the tunnel oxide quality by a low thermal budget dual oxidation for flash memories
1997 / IEEE
By: Sung Tae Ahn; Jonghan Kim;
Variational formulation of Poisson's equation in semiconductor at quasi-equilibrium and its applications
1997 / IEEE
By: Moon-Uhn Kim; Choong-Ki Kim; Kwyro Lee; Chang-Yeol Lee;
Rapid thermal annealing on the characteristics of polysilicon thin-film transistors in practical TFT SRAM process
1997 / IEEE
By: Shou Gwo Wuu; Mong Song Liang; Chii-Wen Chen; Yean Kuen Pang; Kan Yuan Lee;
Simulating the impact of poly-CD wafer-level and die-level variation on circuit performance
1997 / IEEE / 0-7803-3737-9
By: Stine, B.E.; Kibarian, J.K.; Ciplickas, D.; Chung, J.E.; Boning, D.S.;
SEP characterization of 1M EEPROMs from SEEQ and Hybrid Memory
1994 / IEEE / 0-7803-2022-0
By: Guyomard, D.; Liebler, T.; Beaucour, J.; Garnier, P.; Poivey, C.;
Embedded DRAM technologies
1997 / IEEE / 0-7803-4100-7
By: Maeguchi, K.; Yamazaki, K.; Sawada, S.; Momose, H.; Yoshida, T.; Matsuo, K.; Tomioka, K.; Takato, H.; Ishiuchi, H.;
A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance
1997 / IEEE / 0-7803-4100-7
By: Tanzawa, T.; Hagiwara, H.; Satoh, S.; Shirota, R.; Takeuchi, K.;
Low-voltage and high-speed operation for high-density SRAMs by BBC cell
1997 / IEEE / 0-7803-4100-7
By: Morimoto, R.; Honda, H.; Maki, Y.; Miyoshi, H.; Sato, H.; Tsutsumi, K.; Arita, Y.; Wada, T.; Nagaoka, H.;
A 3-D single-electron-memory cell structure with 2F/sup 2/ per bit
1997 / IEEE / 0-7803-4100-7
By: Murai, F.; Mine, T.; Sano, T.; Yano, K.; Ishii, T.; Seki, K.; Kure, T.;
A 0.6 /spl mu/m CMOS pinned photodiode color imager technology
1997 / IEEE / 0-7803-4100-7
By: Shapiro, F.; Hollstein, R.; Arbaugh, L.; Swenson, M.S.; Drowley, C.I.; Domer, S.; Lee, P.P.K.; Lee, T.-H.; Guidash, R.M.; Sackett, D.H.;
Stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics
1998 / IEEE
By: Hemink, G.; Satoh, S.; Aritome, S.; Hatakeyama, K.;
Charge pumping for DRAM retention diagnostic
1997 / IEEE / 0-7803-4205-4
By: Slinkman, J.; Divakaruni, R.; Adkisson, J.;
Device design methodology and reliability strategy for deep sub-micron technology [DRAMs]
1997 / IEEE / 0-7803-4205-4
By: El-Kareh, B.; Divakaruni, R.; Tonti, W.R.;
Approaches to extra low voltage DRAM operation by SOI-DRAM
1998 / IEEE
By: Miyoshi, H.; Eimori, T.; Inuishi, M.; Komori, S.; Inoue, Y.; Arimoto, K.; Sakashita, N.; Nishimura, T.; Shimano, H.; Shimomura, K.; Okuda, F.; Yamaguchi, Y.; Iwamatsu, T.; Morishita, F.; Oashi, T.;
A 255 Mb SDRAM with subthreshold leakage current suppression
1998 / IEEE / 0-7803-4344-1
By: Ohkuma, S.; Nagai, R.; Nanri, S.; Nakamura, M.; Hasegawa, M.; Nakagome, Y.; Horiguchi, M.; Kajigaya, K.; Miyaoka, S.; Kawase, Y.; Tadaki, Y.; Asano, S.; Sekiguchi, T.; Yamada, S.; Yoshida, M.; Kawakita, K.; Akiba, T.; Miyatake, S.; Endoh, H.;
Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a flash EEPROM
1998 / IEEE
By: Schroder, D.K.; Young-Bog Park;
Measurement system for a preliminary characterisation of flash memory cells for multilevel applications
1998 / IEEE / 0-7803-4797-8
By: Landi, C.; Faccio, M.; Bucci, G.; Marotta, G.;
Monitoring of SRAM gate patterns in KrF lithography by ellipsometry
1998 / IEEE / 0-7803-4348-4
By: Nakagawa, K.; Miyata, S.; Nakamura, S.; Arimoto, H.;
Detailed observation of small leak current in flash memories with thin tunnel oxides
1998 / IEEE / 0-7803-4348-4
By: Ajika, N.; Nakashima, M.; Kanno, H.; Ujiie, K.; Manabe, Y.; Nozoe, A.; Kubota, K.; Okuyama, K.; Karashima, T.;
Monitoring method of the tunnel oxide degradation by MOS capacitor
1998 / IEEE / 0-7803-4348-4
By: Hazama, H.;
A negative Vth cell architecture for highly scalable, excellently noise immune and highly reliable NAND flash memories
1998 / IEEE / 0-7803-4766-8
By: Tanaka, T.; Satoh, S.; Takeuchi, K.; Sakui, K.; Imamiya, K.;
Application of a negative sweep voltage to control gate of fresh flash memory devices to facilitate threshold voltage test measurement
1998 / IEEE / 0-7803-4237-2
By: Chan, L.; Zhang, A.Q.; Teo, T.H.; Gong, H.; Chor, E.F.; Cha, C.L.;

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