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Topic: Hspice

Results

A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects
2011 / IEEE
By: Shida Zhong; Al-Hashimi, B.M.; Khursheed, S.;
Modeling Single Event Crosstalk in Nanometer Technologies
2011 / IEEE
By: Yeddula, S.R.; Boorla, V.K.; Sayil, S.;
Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect
2011 / IEEE
By: Raj, B.; Dasgupta, S.; Saxena, A.K.;
Analysis of Common-Mode Noise for Weakly Coupled Differential Serpentine Delay Microstrip Line in High-Speed Digital Circuits
2012 / IEEE
By: Jia-Hung Shiu; Guang-Hwa Shiue; Che-Ming Hsu; Yi-Chin Tsai;
OTA-C Arbitrary-Phase-Shift Oscillators
2012 / IEEE
By: Soliman, A.M.; Jiann-Jong Chen; Yuh-Shyan Hwang; Shu-Hui Tu; Chun-Ming Chang;
Efficient Method for Modeling of SSN Using Time-Domain Impedance Function and Noise Suppression Analysis
2012 / IEEE
By: Yu-Shan Li; Tong-Hao Ding;
Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations
2012 / IEEE
By: Sapatnekar, S.S.; Gupta, S.;
Voltage Driving Scheme Using Three TFTs and One Capacitor for Active-Matrix Organic Light-Emitting Diode Pixel Circuits
2012 / IEEE
By: Chih-Lung Lin; Yu-Cheng Chen; Pin-Yen Kuo; Mao-Hsun Cheng; Wen-Yen Chang; Chia-Che Hung;
Design a Portable Bio-Sensing System for Glucose Measurement
2011 / IEEE / 978-1-61284-709-2
By: Rong-Jian Chen; Hung-Hsi Chang; Han-ning Wu; Jui-Lin Lai;
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM)
2011 / IEEE / 978-1-61284-660-6
By: Smullen, C.W.; Nigam, A.; Stan, M.R.; Gurumurthi, S.; Chen, E.; Mohan, V.;
A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz
2011 / IEEE / 978-1-4577-0803-9
By: Bulusu, A.; Biswas, A.K.; Dasgupta, S.;
The Research of Operational Transconductance Amplifier
2011 / IEEE / 978-1-4577-0860-2
By: Yang Guanghua; Niu Pingjuan; Fu Xiansong; Jin Feiyue; Gao Tiecheng;
Research on floating-gate ISFET biosensor
2011 / IEEE / 978-1-61284-088-8
By: Junqi Yu; Fang Yang; Mingfei Wei; Xiaojuan Zhu;
A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting
2011 / IEEE / 978-1-4244-9789-8
By: Sheikhaei, S.; Maghami, H.; Nanbakhsh, K.; Payandehnia, P.; Masoumi, N.;
Efficient parameters selection for artificial intelligence models of nanoscale MOSFETs
2011 / IEEE / 978-1-4244-9789-8
By: Nohoji, A.H.A.; Zamani, M.; Shokouhifar, M.; Farokhi, F.;
A switched-capacitor differential-capacitance-to-time converter for capacitive sensors
2011 / IEEE / 978-1-61284-857-0
By: Ogawa, S.;
Low power design of a full adder standard cell
2011 / IEEE / 978-1-61284-857-0
By: Jun Wang; Jianping Hu;
Differential capacitance-to-digital converter utilizing time-domain manipulation of intermediate signals
2011 / IEEE / 978-1-61284-857-0
By: Manho Kim; Suhwan Kim; Jong-Kwan Woo; Hyunjoong Lee;
Dual-Vth based double-edge explicit-pulsed level-converting flip-flops
2011 / IEEE / 978-1-4577-0321-8
By: Xia Yin-shui; Wang Qing-xia; Wang Lun-yao;
A new CMOS exponential circuit with extended linear output range
2011 / IEEE / 978-1-4577-0618-9
By: Ozoguz, S.; Saatlo, A.N.;
A leakage reduction scheme for single phase energy-recovery memory using dual threshold CMOS
2011 / IEEE / 978-1-4577-0321-8
By: Jianping Hu; Xiaolei Sheng;
Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits
2011 / IEEE / 978-1-4577-1048-3
By: Jozwiak, L.; Bryk, M.; Kuzmicz, W.;
Adiabatic flip-flops based on CPAL with channel length bias
2011 / IEEE / 978-1-4577-0321-8
By: Yu Zhang; Jianping Hu;
Analog fuzzy controller circuit design for control applications
2011 / IEEE / 978-1-4577-1549-5
By: Hadidi, K.; Khoei, A.; Arvanagi, M.; Ahmadi, A.;
Determining the minimum energy operating point for embedded SRAM memory
2011 / IEEE / 978-1-4577-1921-9
By: Mansour, M.; Yahya, F.B.;
On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS
2011 / IEEE / 978-1-4577-1713-0
By: Lombardi, F.; Jie Han; Pontarelli, S.; Ottavi, M.; Rajderkar, N.;
Multiple polynomial regression for modeling a MOSFET in saturation to validate the Early voltage
2011 / IEEE / 978-1-4577-1417-7
By: Rahman, A.S.M.Z.; Muntasir, T.; Khan, M.A.H.; Layek, M.A.; Acharjee, U.K.;
A sub-�W, 1.0V CMOS temperature sensor circuit insensitive to device parameters
2011 / IEEE / 978-1-4577-0255-6
By: Tamura, H.; Tanno, K.; Sakamoto, R.; Abidin, Z.;
Design and simulation of a switched capacitor ladder filter in a 90nm CMOS technology for WiMAX applications
2011 / IEEE / 978-1-4577-1846-5
By: Mehregan, S.; Shamsi, H.; Nazemi, M.R.;
Investigating the performance of CNFET using 10T SET D-Flip flop
2012 / IEEE / 978-1-4577-1583-9
By: Vishnu, K.S.N.; Raguvaran, E.; Chitra, S.H.;
A digitally programmable calibration circuit for smart sensors
2012 / IEEE / 978-1-4673-1208-0
By: Medrano, N.; Molina-Reyes, J.; Sanz-Pascual, M.T.; Guerrero, E.; Calvo, B.;
Performance evaluation of a 32-nm CNT-OPAMP: Design, characteristic optimization and comparison with CMOS technology
2011 / IEEE / 978-1-61284-908-9
By: Akter, A.; Anam, N.; Zaidi, A.M.; Rahman, F.;
Modeling and SPICE simulation of CdS-pentacene hybrid CMOS TFTs
2012 / IEEE / 978-1-4577-1117-6
By: Gnade, B.E.; Avendano-Bolivar, A.; Salas-Villasenor, A.L.; Mejia, I.; Quevedo-Lopez, M.A.;
A new analog output buffer for data driver of active matrix displays using low-temperature polycrystalline silicon thin-film transistors
2012 / IEEE / 978-1-4673-1188-5
By: Hatzopoulos, A.A.; Siskos, S.; Pappas, I.;
Design and Performance Analysis of Ultra Fast CNFET Comparator and CMOS Implementation Comparison
2012 / IEEE / 978-1-4673-1366-7
By: Shonchoy, N.; Bari, S.M.K.; Khan, A.; Kabir, F.T.;
A Novel Design and Simulation of a Compact and Ultra Fast CNTFET Multi-valued Inverter Using HSPICE
2012 / IEEE / 978-1-4673-1366-7
By: Biswas, S.; Hayat, M.A.; Haque, R.; Jameel, K.M.;
Reduction of leakage-power in CNTFET SRAM cell using stacked sleep technique at 32nm technology
2012 / IEEE / 978-81-909042-2-3
By: Madhavi, B.K.; Rajendra Prasad, S.; Lal Kishore, K.;
Performance Analysis of Dynamic Threshold-Voltage CNTFET for High-Speed Multi-level Voltage Detector
2012 / IEEE / 978-1-4673-1366-7
By: Ahmad, H.M.N.; Arifuzzman, A.K.M.; Biswas, S.; Bari, S.M.K.; Hasan, N.M.A.;
Design of 32nm Forced Stack CNTFET SRAM cell for leakage power reduction
2012 / IEEE / 978-1-4673-0212-8
By: Rajendra Prasad, S.; Lal Kishore, K.; Madhavi, B.K.;
Ultra low-voltage and high speed dynamic and static CMOS precharge logic
2012 / IEEE / 978-1-4673-0821-2
By: Berg, Y.; Mirmotahari, O.;
Programmable calibration circuit for a MIM-ISFET device
2012 / IEEE / 978-1-4577-1772-7
By: Sanz-Pascual, M.T.; Guerrero, E.; Antolin, D.; Calvo, B.; Medrano, N.; Molina-Reyes, J.;
Review of various available spice simulators
2014 / IEEE
By: Agarwal, Vineeta; Pratap, Rajendra; Singh, R K;
High-Speed, Low-Power Quasi Delay Insensitive Handshake Circuits Based on FinFET Technology
2014 / IEEE
By: Zarei, Mohammad Yousef; Mohammadi, Siamak; Mosaffa, Mahdi;
Performance analysis of a high speed, energy efficient 4×4 dynamic RAM cell array using 32nm fully depleted SOI/SON and CNFET
2014 / IEEE
By: Basak, Subhramita; Saha, Priyanka; Sarkar, Subir Kumar;
An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design
2014 / IEEE
By: Dasgupta, S.; Anand, B.; Alam, N.;
Performance analysis of CNTFET based digital logic circuits
2014 / IEEE
By: Chandel, Rajeevan; Shreya, Sonal;
HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design
2014 / IEEE
By: Junsangsri, Pilin; Han, Jie; Lombardi, Fabrizio;
Design of a 32nm independent gate FinFET based SRAM cell with improved noise margin for low power application
2014 / IEEE
By: Rahaman, Mirwaiz; Mahapatra, Rajat;
A 12-ns ECL I/O 256 K*1-bit SRAM using a 1- mu m BiCMOS technology
1988 / IEEE
By: Smith, D.D.; Kertis, R.A.; Bowman, T.L.;
Comparison of current-switched logic gates for high-speed communications applications
1990 / IEEE
By: Ward, S.; Sharratt, A.A.;
High frequency GaAs transconductors and other building blocks for communication
1990 / IEEE
By: Haigh, D.G.; Toumazou, C.;
Multiemitter BiCMOS CML circuits
1992 / IEEE
By: Elrabaa, M.; Elmasry, M.I.;
High mobility cadmium selenide transistors
1991 / IEEE / 0-7803-0213-3
By: Cheung, P.Y.; Judge, C.P.; Wright, S.W.; Lee, M.J.;
A new generation of class AB switched-current memory for analogue sampled-data applications
1991 / IEEE / 0-7803-0050-5
By: Toumazou, C.; Battersby, N.C.;
CMOS multiple-valued logic design. I. Circuit implementation
1993 / IEEE
By: Jain, A.K.; Abd-El-Barr, M.H.; Bolton, R.J.;
Current vs. logic testability of bridges in scan chains
1993 / IEEE / 0-8186-3360-3
By: Figueras, J.; Rodriguez-Montanes, R.; Rubio, A.;
A comparative study of clock distribution approaches for WSI
1993 / IEEE / 0-7803-0867-0
By: Keezer, D.C.; Nigam, N.;
Analysis of latchup and parasitic effects in merged BiCMOS structures
1993 / IEEE
By: Rofail, S.S.; Elmasry, M.I.;
A BiCMOS low distortion tunable OTA for continuous-time filters
1992 / IEEE / 0-7803-0510-8
By: Sanchez-Sinencio, E.; Howe, M.; Ali, M.I.; Ramirez-Angulo, J.;
Schottky merged BiCMOS structures
1994 / IEEE
By: Elmasry, M.I.; Rofail, S.S.;
Coupled electrothermal modeling of microheaters using SPICE
1994 / IEEE
By: Swart, N.R.; Nathan, A.;
Development of read-out circuit and level 2 buffering for multi-channel time measurement chip
1992 / IEEE / 0-7803-0884-0
By: Van Berg, R.; Ekenberg, T.; Williams, H.H.;
Modeling of magnetic field sensitivity of bipolar magnetotransistors using HSPICE
1995 / IEEE
By: Salim, A.; Nathan, A.; Manku, T.;
Improvements in the waveform relaxation method applied to transmission lines
1995 / IEEE
By: Deeley, E.M.; Lau, F.C.M.;
A 3V-125 MHz CMOS continuous-time filter
1993 / IEEE / 0-7803-1281-3
By: Zele, R.H.; Allstot, D.J.; Lee, S.-S.;
A ratio-independent and gain-insensitive algorithmic analog-to-digital converter
1993 / IEEE / 0-7803-1281-3
By: Wu, C.-Y.; Chin, S.-Y.;
An examination of feedback bridging faults in digital CMOS circuits
1993 / IEEE / 0-7803-1281-3
By: Koch, B.K.; Muller-Glaser, K.D.;
T-BIST: A built-in self-test for analog circuits based on parameter translation
1993 / IEEE / 0-8186-3930-X
By: Kaminska, B.; Slamani, M.;
A fast low-power driver for long interconnections in VLSI systems
1994 / IEEE / 0-7803-1915-X
By: Nekili, M.; Bois, G.; Savaria, Y.;
General first and second order current-mode building blocks
1994 / IEEE / 0-7803-1915-X
By: El-Masry, E.I.; Gates, J.; Maundy, B.;
A 155.52 Mb/s receiver chip architecture and its simulation methodology for SONET OC-3 application
1993 / IEEE / 0-7803-1375-5
By: Ming-Tang Shih; Yuh-Diahn Wang; Yung-Chow Peng; Chen-Yi Huang; Hasn-Fong Lin; Jizoo Lin; Chorng-Kuang Wang;
An LCC DC/DC resonant converter designed for applications with variable load and output voltage
1995 / IEEE / 0-7803-2730-6
By: Peracaula, J.; Lamaison, R.M.; Bordonau, J.;
A new DC model of HBT's including self-heating effect suitable for circuit simulators
1995 / IEEE
By: Hajji, R.; Dupuis, J.; Lavallee, S.; Saab, K.; Ghannouchi, F.M.;
CMOS current-mode neural associative memory design with on-chip learning
1996 / IEEE
By: Jeng-Feng Lan; Chung-Yu Wu;
Switched-current analysis program
1996 / IEEE
By: El-Masry, E.I.; Gates, J.W.;
A new direct design for three-input XOR function on the transistor level
1996 / IEEE
By: Sung-Chuan Fang; Wu-Shiung Feng; Jyh-Ming Wang;
Development of an object-oriented knowledge-based system for power electronic circuit design
1996 / IEEE
By: Hulley, L.N.; Shepherd, D.W.; Cumbi, M.J.N.;
Real-time design of FIR filters by feedback neural networks
1996 / IEEE
By: Bhattacharya, D.; Antoniou, A.;
Statistical modelling of Idd testing efficiency of analogue integrated circuits
1995 / IEEE / 0-7803-2516-8
By: Musil, V.;
An AC-AC converter made of two semi direct frequency changers has no limits on the voltage gain
1996 / IEEE / 0-7803-3044-7
By: Ribeiro, E.R.; April, G.-E.; Roy, G.;
A SI incremental A/D converter for IC sensor interfaces
1996 / IEEE / 0-7803-3312-8
By: Yufera, A.; Rueda, A.;
Comments on "Sensitivity analysis of lossy coupled transmission lines" [with reply]
1996 / IEEE
By: Sakagami, I.;
An investigation on the robustness, accuracy and simulation performance of a physics-based deep-submicronmeter BSIM model for analog/digital circuit simulation
1996 / IEEE / 0-7803-3117-6
By: Mansun Chan; Kai Chen; Zhihong Liu; Min-Chie Jeng; Yuhua Cheng; Ping Keung Kox; Chenming Hu;
Real-time synthesis of FIR filters in frequency domain by feedback neural nets
1994 / IEEE / 0-7803-2428-5
By: Bhattacharya, D.; Antoniou, A.;
Computation of switching noise in PCBs for digital packages
1995 / IEEE / 0-7803-3034-X
By: Jong-Gwan Yook; Sakallah, K.A.; Katehi, L.P.; Chandramouli, V.;
Quality considerations in delay fault testing
1995 / IEEE / 0-8186-7156-4
By: Pierzynska, A.; Pilarski, S.;
Area-time-power tradeoffs in parallel adders
1996 / IEEE
By: Owens, R.M.; Irwin, M.J.; Nagendra, C.;
Design of pyroelectric IR readout circuit based on LiTaO/sub 3/ detectors
1996 / IEEE / 0-7803-3073-0
By: Yuan-Liang Kao; Yung-Lung Chin; Tai-Ping Sun; Wen-Yaw Chung;
Simulation of the test process for analogue integrated circuits
1996 / IEEE / 0-7803-3073-0
By: Povazanec, J.; Kaderka, J.; Musil, V.;
A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation
1997 / IEEE
By: Yuhua Cheng; Chenming Hu; Ping Keung Ko; Kai Chen; Min-Chie Jeng; Jianhui Huang; Zhihong Liu; Mansun Chan;
Measurement, modeling and simulation of a high speed digital system using VNA and HSPICE
1996 / IEEE / 0-7803-3277-6
By: Nimmagadda, S.; Dillon, J.; Moncayo, A.;
A flexible statistical model for CAD of submicrometer analog CMOS integrated circuits
1993 / IEEE / 0-8186-4490-7
By: Teng, C.S.; Abel, C.; Michael, C.;
On the design of micropower active resonators and oscillators using log-domain processing
1996 / IEEE / 0-7803-3650-X
By: Pookaiyaudom, S.; Toumazou, C.; Thanachayanont, A.; Ngarmnil, J.;
Neural network based system for testing and diagnostics of analogue integrated circuits
1996 / IEEE / 0-7803-3650-X
By: Kaderka, J.; Musil, V.; Povazanec, J.; Simek, P.;
A FIFO ring performance experiment
1997 / IEEE / 0-8186-7922-0
By: Jones, I.W.; Molnar, C.E.; Lexau, J.K.; Coates, W.S.;
A fast and low power multiplier architecture
1996 / IEEE / 0-7803-3636-4
By: Maaz, M.B.; Abu-Shama, E.; Bayonmi, M.A.;
Optimization of spanning tree carry lookahead adders
1996 / IEEE / 0-8186-7646-9
By: Arndt, L.; Blackburn, J.; Swartzlander, E.E., Jr.;
On using 1-out-of-n codes for (p,q) counter implementations
1996 / IEEE / 0-8186-7646-9
By: McIlhenny, R.; Ercegovac, M.D.;
A current-mode phase-locked loop using a log-domain oscillator
1997 / IEEE / 0-7803-3583-X
By: Payne, A.; Thanachayanont, A.; Pookaiyaudom, S.;
Projections for high performance, minimum power CMOS ASIC technologies: 1998-2010
1997 / IEEE / 0-7803-4283-6
By: Meindl, J.D.; Austin, B.; Bhavnagarwala, A.J.;

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