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Topic: Gate Oxide Thickness

Results

Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis

2011 / IEEE
By: Chopra, K.; Cheng Zhuo; Blaauw, D.; Sylvester, D.;

Comparisons of Performance Potentials of Si and InAs Nanowire MOSFETs Under Ballistic Transport

2012 / IEEE
By: Koba, S.; Takiguchi, N.; Ogawa, M.; Tsuchiya, H.;

Oxide Thinning and Structure Scaling Down Effect of Low-Temperature Poly-Si Thin-Film Transistors

2012 / IEEE
By: Tien-Sheng Chao; Je-Wei Lin; Tsung-Yu Chiang; Ma, W.C.;

Impact of gate length and gate oxide thickness on the relationship of FN-stress induced degradation parameters

2011 / IEEE / 978-1-4577-0115-3
By: Kang, Y.H.; Jung, T.S.; Kim, H.S.; Ryu, Y.K.; Kim, H.U.; Lee, C.W.;

Impact of process variability on universal gates

2012 / IEEE / 978-1-4673-1318-6
By: Khanna, G.; Saonwani, M.; Chandel, R.;

Device characteristics research according to the array EEPROM cell's active pattern difference

2012 / IEEE / 978-1-4673-0238-8
By: Young-sik Choi; Sung-hoon You; Sun-hyun Kim; Sang-bae Yi; Yong-han Roh;

RADFET as a sensor and dosimeter of gamma-ray irradiation

2012 / IEEE / 978-953-233-068-7
By: Nesic, N.T.; Pejovic, M.M.; Pejovic, M.M.;

Current-voltage characteristics CNTFET considering non-ballistic conduction: Effect of gate oxide thickness

2014 / IEEE
By: Mominuzzaman, Sharif Mohammad; Hasan, Mahmudul; Khan, Sabbir Ahmed; Hassan, Rusafa Binte; Deep, Ashfaqul Haq; Rouf, Nirjhor Tahmidur;

A triple low-power voltage output video 8-bit CMOS DAC

1988 / IEEE
By: Fournier, J.M.; Abrial, A.; Lelah, A.; Bouvier, J.; Senn, P.;

Time dependence of interface trap formation in MOSFETs following pulsed irradiation

1988 / IEEE
By: Saks, N.S.; Brown, D.B.; Dozier, C.M.;

0.5 micron CMOS for high performance at 3.3 V

1988 / IEEE
By: Chapman, R.A.; Haken, R.A.; Brown, G.A.; Aur, S.; Bell, D.A.; Wei, C.C.;

Design and performance of submicron MOSFETs on ultra-thin SOI for room temperature and cryogenic operation

1988 / IEEE
By: Woo, J.; Terrill, K.; Vasudev, P.K.;

MOSFET scaling limits determined by subthreshold conduction

1989 / IEEE
By: Pimbley, J.M.; Meindl, J.D.;

A quasi-two-dimensional analytical model for the turn-on characteristics of polysilicon thin-film transistors

1990 / IEEE
By: Lin, P.-S.; Wu, C.-Y.; Guo, J.-Y.;

A closed-loop evaluation and validation of a method for determining the scattering limited carrier velocity in MOSFETs

1990 / IEEE
By: Lee, S.-W.; Chan, T.-Y.;

Distribution phenomena of charged defects and neutral electron traps in process-induced radiation-damaged IGFETs with gate insulators grown at 1000 degrees C and 800 degrees C

1990 / IEEE
By: Reisman, A.; Walters, M.;

PMOS input merged bipolar/sidewall MOS transistors (PBiMOS transistors)

1991 / IEEE
By: Lee, H.-S.; Reif, R.; O, K.;

Gigahertz CMOS/SIMOX circuits

1988 / IEEE
By: Stout, C.; McFarland, W.; Kang, J.; Colinge, J.P.; Walker, R.;

Choice of power-supply voltage for half-micrometer and lower submicrometer CMOS devices

1990 / IEEE
By: Kakumu, M.; Hashimoto, K.; Kinugawa, M.;

A high-performance 0.25- mu m CMOS technology. I. Design and characterization

1992 / IEEE
By: Taur, Y.; Wordeman, M.R.; Davari, B.; Chang, W.-H.; Rodriguez, M.D.; Hsu, C.C.-H.;

Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model

1992 / IEEE
By: Wann, H.C.; Moon, J.E.; Parke, S.A.; Hu, C.; Ko, P.K.;

89-GHz f/sub T/ room-temperature silicon MOSFETs

1992 / IEEE
By: Mansfield, W.M.; Watts, R.K.; Early, K.; Morris, M.D.; Chin, G.M.; Westerwick, E.H.; Mulgrew, P.; Tennant, D.M.; Rafferty, C.S.; Pinto, M.R.; Park, B.G.; Kim, Y.O.; Jeon, D.Y.; Lee, K.F.; Yan, R.-H.; Ourmazd, A.; Swartz, R.G.; Bokor, J.; Voshchenkov, A.M.;

Time dependence of fully-depleted SOI MOSFETs subthreshold current

1991 / IEEE / 0-7803-0184-6
By: Chan, T.; Solomon, R.; Chen, J.; Eraghi, F.A.; Hu, C.; Ko, P.;

Performance of 0.8 mu m-SOIMOSFETs fabricated in high quality laser recrystallized SOI

1991 / IEEE / 0-7803-0184-6
By: Inoue, Y.; Sugahara, K.; Wouters, D.J.; Ipposhi, T.; Akasaka, Y.; Nishimura, T.;

Comparison of ultralow specific on-resistance UMOSFET structures

1992 / IEEE
By: Venkatraman, P.; Syau, T.; Baliga, B.J.;

Experimental characterization of the diode-type polysilicon loads for CMOS SRAM

1993 / IEEE
By: Kalnitsky, A.; Chen, C.E.D.; Li, J.;

Characteristics of MOS capacitors of BF/sub 2/ or B implanted polysilicon gate with and without POCl/sub 3/ co-doped

1993 / IEEE
By: Hsieh, J.C.; Tseng, F.C.; Lin, M.-S.; Tsai, N.S.; Chen, C.W.; Fang, Y.K.;

Decrease of gate oxide dielectric constant in tungsten polycide gate processes

1993 / IEEE
By: Yang, F.H.; Wulu, H.-C.; Cherng, Y.C.; Lu, C.Y.;

High-performance sub-quarter-micrometer PMOSFET's on SOI

1993 / IEEE
By: King, J.; Parke, S.; Assaderaghi, F.; Hu, C.; Ko, P.K.; Chen, J.;

Hot-carrier effects in surface-channel PMOSFETs with BF/sub 2/- or boron-implanted gates

1991 / IEEE / 0-7803-0243-5
By: Mogami, T.; Fukuma, M.; Sakai, I.; Johansson, L.E.G.;

High-performance 0.5 mu m CMOS technology for logic LSIs with embedded large capacity SRAMs

1991 / IEEE / 0-7803-0243-5
By: Shibata, H.; Matsuno, T.; Matsunaga, T.; Shinagawa, H.; Kasai, K.; Toyoshima, Y.; Hayashida, H.; Yoshinari, H.; Norishima, M.; Eguchi, T.; Hashimoto, K.;

A reliable bi-polarity write/erase technology in flash EEPROMs

1990 / IEEE
By: Kirisawa, R.; Shirota, R.; Aritome, S.; Masuoka, F.; Sakui, K.; Nakayama, R.; Endoh, T.;

Threshold voltage model for deep-submicrometer MOSFETs

1993 / IEEE
By: Jeng, M.-C.; Chan, T.-Y.; Huang, J.-H.; Hu, C.; Liu, Z.-H.; Cheng, Y.C.; Ko, P.K.;

Scaling theory for double-gate SOI MOSFET's

1993 / IEEE
By: Arimoto, Y.; Horie, H.; Tosaka, Y.; Tanaka, T.; Suzuki, K.;

A low power 0.25 mu m CMOS technology

1992 / IEEE / 0-7803-0817-4
By: Pomp, H.; Manders, W.; Lifka, H.; Juffermans, C.A.H.; Paulzen, G.; Woltjer, R.; Woerlee, P.H.; Walker, A.J.;

A physical model for MOSFET output resistance

1992 / IEEE / 0-7803-0817-4
By: Jeng, M.C.; Liu, Z.H.; Huang, J.H.; Hu, C.; Ko, P.K.;

The effect of plasma-induced oxide and interface degradation on hot carrier reliability

1994 / IEEE / 0-7803-1357-7
By: Noguchi, K.; Okumura, K.;

A pass transistor design methodology for 256 Mbit DRAM and beyond

1994 / IEEE / 0-7803-1921-4
By: Chen, I.-C.; Rodder, M.; Mozumder, P.K.; Liu, J.; Chatterjee, A.;

Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's

1994 / IEEE
By: Mizuno, T.; Okumtura, J.; Toriumi, A.;

Polysilicon gate depletion effect on deep-submicron circuit performance

1994 / IEEE / 0-7803-1867-6
By: Chunlin Liang; Lin, W.W.;

Self-heating effects in SOI MOSFET's operated at low temperature

1993 / IEEE / 0-7803-1346-1
By: Balestra, F.; Jomaah, J.; Ghibaudo, G.;

Analysis of gate oxide thickness hot carrier effects in surface channel P-MOSFET's

1995 / IEEE
By: Cheng-Liang Huang; Mistry, K.R.; Doyle, B.S.;

Determination of ultra-thin gate oxide thicknesses for CMOS structures using quantum effects

1994 / IEEE / 0-7803-2111-1
By: Rios, R.; Arora, N.D.;

Tunneling gate oxide approach to ultra-high current drive in small geometry MOSFETs

1994 / IEEE / 0-7803-2111-1
By: Momose, H.S.; Iwai, H.; Saito, M.; Nakamura, S.; Ohguro, T.; Yoshitomi, T.; Ono, M.;

Impact of boron diffusion through O/sub 2/ and N/sub 2/O gate dielectrics on the process margin of dual-poly low power CMOS

1994 / IEEE / 0-7803-2111-1
By: Green, M.L.; Baumann, F.H.; Manchanda, L.; Krisch, K.S.; Ourmazd, A.; Feldman, L.C.; Brasen, D.;

A study on hot carrier effects on N-MOSFETs under high substrate impurity concentration

1995 / IEEE
By: Yoshitomi, T.; Saito, M.; Ono, M.; Iwai, H.; Momose, H.S.; Ohguro, T.; Fiegna, C.;

Analytical models for n/sup +/-p/sup +/ double-gate SOI MOSFET's

1995 / IEEE
By: Suzuki, K.; Sugii, T.;

Temperature-dependent hole and electron mobility models for CMOS circuit simulation

1995 / IEEE
By: Kwyro Lee; Kyeong-Sik Min;

Manufacturability improvements of inductively coupled plasma etch chambers in PVD tools

1995 / IEEE / 0-7803-2713-6
By: Bonner, E.A.; Berti, A.C.;

Correlation between inversion layer mobility and surface roughness measured by AFM

1996 / IEEE
By: Snyder, J.P.; Heng-Chih Lin; Fang, S.J.; Yamanaka, T.; Helms, C.R.;

Impact of oxide thickness on SEGR failure in vertical power MOSFETs; development of a semi-empirical expression

1995 / IEEE
By: Allenspach, M.; Mouret, I.; Burton, D.I.; Wheatley, C.F.; Brews, J.; Pease, R.L.; Titus, J.L.; Galloway, K.; Schrimpf, R.;

Wafer level reliability procedures to monitor gate oxide quality using V ramp and J ramp test methodology

1995 / IEEE / 0-7803-2705-5
By: Kapoor, A.K.; Lie, L.N.;

A new technique to measure thin oxide thickness in IC manufacturing

1995 / IEEE / 0-7803-2705-5
By: Wang, L.; Nayak, D.K.; Rakkhit, R.;

A poly-silicon TFT model for circuit simulation

1995 / IEEE / 0-7803-3062-5
By: Xudong Guan; Ruqi Han; Xiaoyan Liu;

Effects of quantization on the electrical characteristics of deep submicron p- and n-MOSFETs

1996 / IEEE / 0-7803-3342-X
By: Pinto, M.R.; Shih, W.K.; Bude, J.; Jallepalli, S.; Tasch, A.F., Jr; Maziar, C.M.;

A 30-V P-channel trench gated DMOSFET with 900 /spl mu//spl Omega/-cm/sup 2/ specific on-resistance at 2.7 V

1996 / IEEE / 0-7803-3106-0
By: Yilmaz, H.; Darwish, M.; Grabowski, W.; Williams, R.K.; Owyang, K.; Chang, M.;

Minimizing floating-body-induced threshold voltage variation in partially depleted SOI CMOS

1996 / IEEE
By: Bair, L.A.; Antoniadis, D.A.; Wei, A.;

A test chip for MOS transistor capacitance characterization

1995 / IEEE / 0-7803-2065-4
By: Lorival, R.; Nouet, P.;

Hot-carrier-injection (HCI) immunity under high drain stress of thin-film SOI n-MOSFETs fabricated on SIMOX and BESOI substrates

1994 / IEEE / 0-7803-2406-4
By: Woo, J.; Foerstner, J.; Racanelli, M.; Bor-Yuan Hwang; Huang, W.M.; Wang, J.;

Gate-oxide thickness effects on hot-carrier-induced degradation in n-MOSFETs

1996 / IEEE / 0-7803-3268-7
By: Gu, Y.; Yuan, J.S.;

A statistical methodology as applied to a 256 Mbit DRAM pass transistor design

1996 / IEEE
By: Chatterjee, A.; Mozumder, P.K.;

Drain current enhancement due to velocity overshoot effects and its analytic modeling

1996 / IEEE
By: Hong-Shick Min; Young-June Park; Jai-Hyuk Song;

A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation

1997 / IEEE
By: Yuhua Cheng; Chenming Hu; Ping Keung Ko; Kai Chen; Min-Chie Jeng; Jianhui Huang; Zhihong Liu; Mansun Chan;

CMOS technology for ultra-low power circuit applications

1997 / IEEE / 0-7803-3844-8
By: Maimon, J.; Whittaker, D.R.; Henly, W.B.; Salomonson, C.D.;

Gate tunneling current in thin oxide MOSFET

1996 / IEEE / 0-7803-3388-8
By: Shaari, S.; Karim, M.F.; Majlis, Y.;

Optimizing quarter and sub-quarter micron CMOS circuit speed considering interconnect loading effects

1997 / IEEE
By: Wollesen, D.L.; Min Ren Lin; Peng Fang; Chenming Hu; Kai Chen;

Quick characterization of statistical variations and sensitivity for speed and power consumption within a wafer of sub-micron CMOS

1997 / IEEE / 0-7803-3737-9
By: Lee, M.M.-O.; Asada, K.;

Impact of nitrogen implant prior to the gate oxide growth on transient enhanced diffusion

1997 / IEEE / 0-7803-4100-7
By: Vuong, H.-H.; Kamgar, A.; Clemens, J.T.; Rafferty, C.S.; Liu, C.T.;

RF noise in 1.5 nm gate oxide MOSFETs and the evaluation of the NMOS LNA circuit integrated on a chip

1998 / IEEE / 0-7803-4770-6
By: Tanimoto, H.; Katsumata, Y.; Morimoto, T.; Nakamura, S.; Kimijima, H.; Yoshitomi, T.; Iwai, H.; Morifuji, E.; Otaka, S.; Fujimoto, R.; Momose, H.S.; Ohguro, T.;

Total dose hardness of three commercial CMOS microelectronics foundries

1997 / IEEE / 0-7803-4071-X
By: Lacoe, R.C.; Osborn, J.V.; Yabiku, G.; Mayer, D.C.;

Impact of VLSI design rules on high voltage (2000 V) IGBTs/ESTs

1998 / IEEE / 0-7803-4752-8
By: Sawant, S.; Baliga, B.J.;

Slight gate oxide thickness increase in PMOS devices with BF₂ implanted polysilicon gate

1998 / IEEE
By: Prasad, S.; Ying Shi; Jiunn-Yann Tsai; Rakkhit, R.; Yeh, S.W.-C.;

SOI and device scaling

1998 / IEEE / 0-7803-4500-2
By: Hu, C.;

Reduction of crystalline defects to 50/cm/sup 2/ in epitaxial layers over porous silicon for ELTRAN/sup R/ process

1998 / IEEE / 0-7803-4500-2
By: Sato, N.; Yonehara, T.; Nakayama, J.; Ito, M.; Matsumura, S.; Ishii, S.;

Analysis of hot-carrier-induced degradation in deep submicron Unibond and SIMOX N-MOSFETs using charge pumping and noise techniques

1998 / IEEE / 0-7803-4500-2
By: Renn, S.H.; Balestra, F.; Raynaud, C.; Jomaah, J.;

Characterization of plasma induced damage using transient current measurements

1998 / IEEE / 0-9651577-2-5
By: Chung, A.; Ramkumar, K.; Bamnolker, H.; Petti, C.; Balasinski, A.;

Study of direct-tunneling gate oxides for CMOS applications

1998 / IEEE / 0-9651577-2-5
By: Katsumata, Y.; Nakamura, S.-I.; Momose, H.S.; Iwai, H.;

Calculating plasma damage as a function of gate oxide thickness

1998 / IEEE / 0-9651577-2-5
By: Cheung, N.W.; Linder, B.P.;

Effect of device type and plasma process on the oxide thickness dependence of plasma-induced charging damage

1998 / IEEE / 0-9651577-2-5
By: Dao, T.; Brozek, T.;

Stress-induced leakage current due to charging damage: gate oxide thickness and gate poly-Si etching condition dependence

1998 / IEEE / 0-9651577-2-5
By: Melaku, Y.; Kennard, M.; Park, D.; Hu, C.; King, T.-J.; Benjamin, N.;

Methodology of MOSFET characteristics fluctuation description using BSIM3v3 SPICE model for statistical circuit simulations

1998 / IEEE / 0-7803-4338-7
By: Kasai, K.; Okayama, Y.; Oishi, A.; Azuma, A.; Toyoshima, Y.;

Controlling mesh effects in integrated process and device simulation

1998 / IEEE / 0-7803-4338-7
By: Duane, M.; Axelrad, V.;

Analysis of gate tunneling current in ultra-thin oxide MOSFET's

1998 / IEEE / 0-7803-4995-4
By: Bowen, C.; Chang, M.-C.; Erdogan, M.U.; Shichijo, H.; Seitchik, J.; Chatterjee, A.;

CMOS hot carrier lifetime improvement from deuterium anneal

1998 / IEEE / 0-7803-4995-4
By: Fang, P.; Tao, J.; Rosenbaum, E.; Li, E.;

Direct measurement of l/sub eff/ and channel profile in MOSFETs using 2-D carrier profiling techniques

1998 / IEEE / 0-7803-4774-9
By: Stephenson, R.; Wolf, P.D.; Vandervorst, W.; De Meyer, K.; Badenes, G.; Jansen, Ph.; Biesemans, S.;

Straddle-gate transistor: changing MOSFET channel length between off- and on-state towards achieving tunneling-defined limit of field-effect

1998 / IEEE / 0-7803-4774-9
By: Tiwari, S.; Solomon, P.M.; Welser, J.J.;

Fully depleted CMOS/SOI device design guidelines for low-power applications

1999 / IEEE
By: Ko, P.K.; Fung, S.K.H.; Chan, M.; Chan, P.C.H.; Banna, S.R.;

An efficient and accurate compact model for thin-oxide-MOSFET intrinsic capacitance considering the finite charge layer thickness

1999 / IEEE
By: Jin, X.; Liu, W.; Hu, C.; King, Y.;

Analysis of snapback behavior on the ESD capability of sub-0.20 /spl mu/m NMOS

1999 / IEEE / 0-7803-5220-3
By: Ramaswamy, S.; Vasanth, K.; Gupta, V.; Amerasekera, A.;

Improved method for the oxide thickness extraction in MOS structures with ultra-thin gate dielectrics

1999 / IEEE / 0-7803-5270-X
By: Vincent, E.; DeSalvo, B.; Devoivre, T.; Bruyere, S.; Ghibaudo, G.;

Study on ultra-thin gate dielectrics: surface preparation and reliability

1998 / IEEE / 0-7803-4306-9
By: Qian He; Xu Qiuxia; Chai Shumin; Jia Lin;

Effect of plasma density and uniformity, electron temperature, process gas, and chamber on electron shading damage

1999 / IEEE / 0-9651577-3-3
By: Siu, S.; Patrick, R.; Colombo, P.; Alba, S.; Valentini, G.; Vahedi, V.;

Plasma induced damage from HDP process on the ultra-thin gate oxide

1999 / IEEE / 0-9651577-3-3
By: Yin Jin; Shoumian Chen; Perera, C.; Sudijono, J.; Susilo, F.; Jianqing Wen; Kumar, A.V.; Xu Zeng;

Annealing of plasma charging damage and residual degradation in MOS transistors

1999 / IEEE / 0-9651577-3-3
By: Brozek, T.;

Effect of wafer bias frequency on microtrenching during high selective gate etching

1999 / IEEE / 0-9651577-3-3
By: Morioka, H.; Abe, N.; Ishida, T.; Hasegawa, A.;

High performance fully and partially depleted poly-Si surrounding gate transistors

1999 / IEEE / 4-930813-93-X
By: Hyun-Jin Cho; Plummer, J.D.;

Temperature acceleration of oxide breakdown and its impact on ultra-thin gate oxide reliability

1999 / IEEE / 4-930813-93-X
By: Pangon, N.; Degraeve, R.; Naem, A.; Groeseneken, G.; Nigam, T.; Kaczer, B.;

C-V and gate tunneling current characterization of ultra-thin gate oxide MOS (t/sub ox/=1.3-1.8 nm)

1999 / IEEE / 4-930813-93-X
By: Dutton, R.W.; Jung-Suk Goo; Zhiping Yu; Tae-Young Oh; Bayoumi, A.; Chang-Hoon Choi; Vook, D.; Voorde, P.V.; Min Cao;

Impact of extrinsic and intrinsic parameter variations on CMOS system on a chip performance

1999 / IEEE / 0-7803-5632-2
By: Bowman, K.A.; Meindl, J.D.; Eble, J.C.; Xinghai Tang;

Comparison of charge control technologies for advanced high current ion implantation systems

1999 / IEEE / 0-7803-4538-X
By: Mason, P.; Santiesteban, R.; Mack, M.E.; Sawyer, W.; Erokhin, Y.; Treible, R.; Persson, E.;

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