Your Search Results

Use materials about this topic in your textbook!

AcademicPub holds over eight million pieces of educational content - such as case studies and journal articles - for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!

Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

Topic: Dynamic Random Access Memory

Results

Prefetch-Aware Memory Controllers

2011 / IEEE
By: Mutlu, O.; Chang Joo Lee; Patt, Y.N.; Narasiman, V.;

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

2012 / IEEE
By: Mutlu, O.; HanBin Yoon; Jichuan Chang; Meza, J.; Ranganathan, P.;

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

2012 / IEEE
By: Gyung-Su Byun; Therdsteerasukdi, K.; Chang, M.F.; Cong, J.; Reinman, G.; Ir, J.;

Designing Chip-Level Nanophotonic Interconnection Networks

2012 / IEEE
By: Joshi, A.; Batten, C.; Asanovic, K.; Stojanovic, V.;

DRAM Data Retention and Cell Transistor Threshold Voltage Reliability Improved by Passivation Annealing Prior to the Deposition of Plasma Nitride Layer

2012 / IEEE
By: Wang, D.H.-L.; Chia-Ming Yang; Chao-Sung Lai; Chung-Yuan Lee;

A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration

2012 / IEEE
By: Cristoloveanu, S.; Zaslavsky, A.; Le Royer, C.; Wan, J.;

DRAM failure cases under hot-carrier injection

2011 / IEEE / 978-1-4577-0158-0
By: ShiJie Wen; Chia, P.; Sanghyeon Baeg; Wong, R.;

Memory controllers for high-performance and real-time MPSoCs requirements, architectures, and future trends

2011 / IEEE / 978-1-4503-0715-4
By: Tei-Wei Kuo; Yuan-Hao Chang; Goossens, K.; Dutoit, D.; Vivet, P.; Clermidy, F.; Po-Chun Huang; Akesson, B.; Wingard, D.;

PRET DRAM controller: Bank privatization for predictability and temporal isolation

2011 / IEEE / 978-1-4503-0715-4
By: Liu, I.; Reineke, J.; Lee, E.A.; Sungjun Kim; Patel, H.D.;

The DIMM tree architecture: A high bandwidth and scalable memory system

2011 / IEEE / 978-1-4577-1954-7
By: Reinman, G.; Ir, J.; Gyung-Su Byun; Therdsteerasukdi, K.; Chang, M.F.; Cong, J.;

Adjustable supply voltages and refresh cycle for process variations, temperature changes, and device degradation adaptation in 1T1C embedded DRAM

2011 / IEEE / 978-1-4673-0469-6
By: Le-Nguyen Tran; Aljumah, A.; Eltawil, A.M.; Kurdahi, F.J.;

Design and implementation of 32nm FINFET based 4� SRAM cell array using 1-bit 6T SRAM

2011 / IEEE / 978-1-4673-0074-2
By: Lourts Deepak, A.; Dhulipalla, L.;

Comparison of innovation diffusion models: A case study on the DRAM industry

2012 / IEEE / 978-1-4673-1506-7
By: You Wei Dong; Yu, Jing Rung; Tseng, Fang-Mei; Yi Hsuan Chang;

A variable-size shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOS

1988 / IEEE
By: Warnock, J.; Megdanis, A.; Mauer, J.; Noble, W.; Taur, Y.; Furukawa, T.; Koburger, C.; Davari, B.;

Fully planarized 0.5 mu m technologies for 16-Mb DRAM

1988 / IEEE
By: Fujii, A.; Miyatake, H.; Shibano, T.; Itoh, H.; Fujiwara, K.; Tsutsumi, T.; Ozaki, H.; Eimori, T.; Wakamiya, W.; Katoh, T.; Satoh, S.;

A new stacked capacitor DRAM cell characterized by a storage capacitor on a bit-line structure

1988 / IEEE
By: Itoh, K.; Kure, T.; Kawamoto, Y.; Kimura, S.; Hasegawa, N.; Sunami, H.; Takeda, E.; Aoki, M.; Etoh, J.;

A video codec LSI for high-definition TV systems with one-transistor DRAM line memories

1989 / IEEE
By: Kitagaki, K.; Oto, T.; Takada, T.; Oku, T.; Hatanaka, N.; Sue, H.; Odaka, T.; Fuji, H.; Demura, T.;

A 4-Mbit trench DRAM technology functional test manufacturing/characterization strategy

1990 / IEEE
By: Long, C.W.; Voldman, S.H.;

Array diagnostic monitor-a DRAM technology development vehicle

1990 / IEEE
By: Newhart, R.E.; Richard, G.; Sprogis, E.; Paggi, M.;

Novel test structure to study junction leakage current

1990 / IEEE
By: Koike, N.; Tominaga, K.;

TLM: a trench leakage monitor for a four megabit DRAM technology

1990 / IEEE
By: Long, C.W.; Voldman, S.H.;

Trends in megabit DRAM circuit design

1990 / IEEE
By: Itoh, K.;

Dynamic systolic associative memory chip

1990 / IEEE / 0-8186-9089-5
By: Lipovski, G.J.;

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

1992 / IEEE
By: Saeki, T.; Sakao, M.; Kunio, T.; Shibahara, K.; Hada, H.; Kasai, N.; Tanigawa, T.; Ishijima, T.; Takada, M.; Aimoto, Y.; Koike, H.; Takeshima, T.; Tanabe, A.; Okuda, T.; Koyama, K.; Murotani, T.; Ohya, S.; Nozue, H.; Miyamoto, H.;

Texas Instruments' 4 Mb DRAM-a new, faster generation of DRAM

1991 / IEEE / 0-7803-0085-8
By: Rhodine, C.W.;

A video pattern generator for vision test

1992 / IEEE / 0-7803-0510-8
By: Cibis, G.; Abu-Saymeh, D.S.; Obaidat, M.S.; Pierce, D.;

256 Mb DRAM technologies for file applications

1993 / IEEE / 0-7803-0987-1
By: Shukuri, S.; Sagara, K.; Sakai, T.; Tachibana, T.; Aoki, M.; Kawase, Y.; Aikiba, T.; Kawahara, T.; Kawaijiri, Y.; Horiguchi, M.; Kitsukawa, G.; Nishida, T.; Kure, T.; Yamashita, H.; Kisu, T.; Yokoyama, N.; Hasegawa, N.; Nagai, R.;

Future technological and economic prospects for VLSI

1993 / IEEE / 0-7803-0987-1
By: Komiya, H.;

Design for reliability, testability and manufacturability of memory chips

1993 / IEEE / 0-7803-0943-X
By: Stapper, C.H.; Kalter, H.L.; Ellis, W.F.;

A proposed SEU tolerant dynamic random access memory (DRAM) cell

1994 / IEEE
By: Gulati, K.; Massengill, L.W.; Agrawal, G.R.;

A multi-channel time-to-digital converter chip for drift chamber readout

1995 / IEEE / 0-7803-3180-X
By: Levi, M.E.; Flasck, J.; Dow, S.; DeBusschere, D.; Kirsten, F.; Chau, A.; Santos, D.M.; Su, E.;

Floating-body concerns for SOI dynamic random access memory (DRAM)

1996 / IEEE / 0-7803-3315-2
By: Mandelman, J.A.; Hanafi, H.I.; Gautier, J.; Kalter, H.L.; Dennard, R.H.; DeBrosse, J.K.; Barth, J.E.;

Sol-gel processing SrTiO/sub 3/ thin films for dynamic random access memory applications

1996 / IEEE / 0-7803-2695-4
By: Zhong-Yan Meng; Xin-Shan Li; Qing-Feng Liu;

Flexible test mode approach for 256-Mb DRAM

1997 / IEEE
By: Asao, Y.; Fujii, S.; Wordeman, M.R.; Yoshida, M.; Hara, T.; Krsnik, B.; DeBrosse, J.K.; Hing Wong; Kirihata, T.; Watanabe, Y.;

SLDRAM: high-performance, open-standard memory

1997 / IEEE
By: Gillingham, P.; Vogley, B.;

The analysis of competitive factors of integrated circuit industry in Taiwan-a case study of DRAM (dynamic random access memory)

1997 / IEEE / 0-8186-7743-0
By: Yuan, B.J.C.; Wang-Yiu Yuen;

On the retention time distribution of dynamic random access memory (DRAM)

1998 / IEEE
By: Hamamoto, T.; Sawada, S.; Sugiura, S.;

Power analysis of DRAMs

1998 / IEEE / 0-8186-8277-9
By: Vollrath, J.; Stahl, E.; Huebl, M.;

Digital still cameras

1999 / IEEE
By: Sugiura, H.; Kuno, T.; Matoba, N.;

A 390-mm/sup 2/, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture

1999 / IEEE
By: Selz, M.; Poechmueller, P.; Hug, M.A.; Reith, A.M.; Sotraska, D.W.; Hsu, L.L.-C.; Daniel, G.; Guay, K.P.; Hanson, D.R.; Weinfurtner, O.; Netis, D.G.; Terletzki, H.; Ross, J.M.; Frankowsky, G.; Ji, B.; Mueller, G.; Kirihata, T.; Wordeman, M.R.; Hoenigschmid, H.;

Embedded DRAM: more than just a memory

2000 / IEEE
By: Diodato, P.W.;

Development of a F/sub 2/ laser with high repetition rate for optical lithography below 100-nm node

2000 / IEEE / 1-55752-634-6
By: Shio, K.; Nagai, S.; Mizoguchi, H.; Wakabayashi, O.; Fujimoto, J.; Takehisa, K.;

Device scaling limits of Si MOSFETs and their application dependencies

2001 / IEEE
By: Hon-Sum Philip Wong; Taur, Y.; Solomon, P.M.; Nowak, E.; Dennard, R.H.; Frank, D.J.;

A new method for predicting distribution of DRAM retention time

2001 / IEEE / 0-7803-6587-9
By: Moniwa, M.; Kamohara, S.; Yamada, R.-I.; Mori, Y.; Yamanaka, O.; Ohyu, K.;

Improvement of p/sup +/ contact resistance through optimal boron distribution TiSi/sub 2//P/sup +/ interface for 0.18 /spl mu/m DRAM technology and beyond

2000 / IEEE / 0-7803-6462-7
By: Jeong Su Han; Il Gweon Kim;

2 metal layer tape package for improving the performance of high speed DRAM

2001 / IEEE / 0-7803-7038-4
By: Jung-Jin Kim; Dong-Ho Lee; Tae-Sub Chang; Mee-Hyun Ahn;

Electrical characteristics of CeO/sub 2/ buffer layer for a FRAM

2000 / IEEE / 0-7803-5940-2
By: Junsin Yi; Donggeun Jung; Hoongjoo Lee; Yonghan Roh; Sunghoon Kim; Sukwon Choi; Kyunghae Kim;

Ultraviolet laser repair of advanced semiconductor memory devices

2001 / IEEE / 1-55752-662-1
By: Nilsen, B.E.; Baird, B.W.; Ho Wai Lo; Hainsey, R.F.;

On placement and routing of wafer scale memory

2001 / IEEE / 0-7803-7057-0
By: Li-An Sung; Tai-Sheng Feng; Jiin-Chuan Wu; Jing-Yang Jou; Yoh-Wen Chang; Iris Hui-Ru Jiang;

High-speed DRAM interface

2002 / IEEE
By: Yoo, C.;

Induced error-correcting code for 2 bit-per-cell multi-level DRAM

2001 / IEEE / 0-7803-7150-X
By: Polianskikh, B.; Zilic, Z.;

Nanotechnology goals and challenges for electronic applications

2002 / IEEE
By: Bohr, M.T.;

Technology scaling trends and accelerated testing for soft errors in commercial silicon devices

2003 / IEEE / 0-7695-1968-7
By: Baumann, R.;

Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design

2003 / IEEE / 1-58113-688-9
By: Taewhan Kim; Yoonseo Choi;

A study on the VLSI implementation of ECC for embedded DRAM

2003 / IEEE / 0-7803-7781-8
By: Gao, W.; Simmons, S.;

Impact of three-dimensional transistor on the pattern area reduction for ULSI

2003 / IEEE
By: Watanabe, S.;

Soft faults and the importance of stresses in memory testing

2004 / IEEE / 0-7695-2085-5
By: Al-Ars, Z.; van de Goor, A.J.;

Real impact of dynamic operation stress during burn-in on DRAM retention time

2004 / IEEE
By: Se-Kyeong Choi; Il-Gweon Kim; Joo-Seog Park; Jin-Hyeok Choi;

Variability in measured SEE sensitivity associated with design and fabrication iterations

2003 / IEEE / 0-7803-8127-0
By: Koga, R.; Tran, V.; Yu, P.; Crawford, K.; LaLumondiere, S.; George, J.; Crain, S.;

Correlation between proton and heavy-ion SEUs in commercial memory devices

2003 / IEEE / 0-7803-8127-0
By: Ikeda, N.; Shindo, H.; Iide, Y.; Asai, H.; Nemoto, N.; Kuboyama, S.; Nashiyama, I.; Chiba, K.; Sugimoto, K.; Matsuda, S.;

Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications

2004 / IEEE
By: Bronner, G.; Pochmuller, P.; Divakaruni, R.; Voigt, P.; Beintner, J.; Chidambarrao, D.; Knorr, A.; Li, Y.;

Beyond nanoscale DRAM and flash challenges and opportunities for research in emerging memory devices

2004 / IEEE / 0-7803-8369-9
By: Tran, L.C.;

Effects of bit line coupling on the faulty behavior of DRAMs

2004 / IEEE / 0-7695-2134-7
By: van de Goor, Ad.J.; Hamdioui, S.; Al-Ars, Z.;

A framework for profiling multiprocessor memory performance

2004 / IEEE / 0-7695-2152-5
By: Olszewski, B.; Teller, P.J.; Acosta, J.; Villa, D.; Morgan, T.;

Uniqueness in activation energy and charge-to-breakdown of highly asymmetrical DRAM Al/sub 2/O/sub 3/ cell capacitors

2004 / IEEE
By: Ditali, A.; Banerjee, P.;

Performance evaluations of stacked CSP memory modules

2004 / IEEE / 0-7803-8582-9
By: Solberg, V.; Gray, G.;

A study of the effects of microwave electromagnetic radiation on dynamic random access memory operation

2004 / IEEE / 0-7803-8443-1
By: Kenneth, O.; Bohorquez, J.L.;

Extending storage dielectric scaling limit by reoxidizing nitrided NO dielectric for trench DRAM

2005 / IEEE
By: Ku, A.; Lai, S.; Kuo, R.; Hsieh, E.; Yung-Hsien Wu;

Material impact on FBGA package reliability

2005 / IEEE / 0-7803-9085-7
By: Kong, F.; Koh, W.;

In-flight measurement of space radiation effects on commercial DRAM

2004 / IEEE / 0-7803-8656-6
By: Ichikawa, S.; Sasada, T.; Kanai, T.;

Challenges of DRAM and flash scaling - potentials in advanced emerging memory devices

2004 / IEEE / 0-7803-8511-X
By: Tran, L.C.;

The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond

2005 / IEEE / 0-7803-9058-X
By: Kim, J.Y.; Woo, D.S.; Kinam Kim; Park, Y.J.; Jin, G.Y.; Kim, H.S.; Choi, W.T.; Cho, M.H.; Lee, B.H.; Kim, Y.I.; Jung, M.Y.; Lee, Y.S.; Kim, Y.R.; Park, S.J.; Lee, C.S.; Han, D.H.; Huh, M.; Kim, D.H.; Kim, D.I.; Hwang, Y.S.; Song, S.S.; Oh, H.J.; Kim, H.J.; Kim, S.E.; Park, B.J.; Kwon, J.M.; Shim, M.S.; Ha, G.W.; Song, J.W.; Kang, N.J.; Park, J.M.; Hwang, H.K.;

Automatic generated built-in-self-test for embedded memory

2004 / IEEE / 0-7803-8909-3
By: Banerjee, S.; Chowdhury, D.R.; Mukhopadhyay, D.;

Hierarchical built-in self-test for system-on-chip design

2005 / IEEE / 0-7803-9328-7
By: Chen, H.H.;

Nanoscale capacitors based on metal-insulator-carbon nanotube-metal (MICNM) structures

2005 / IEEE / 0-7803-9203-5
By: Cha, S.N.; Jang, J.E.; Amaratunga, G.A.J.; Haskot, D.G.; Kang, D.J.; Choi, Y.;

A novel low area and high performance programmable FIR filter design using dynamic random access memory

2005 / IEEE / 0-7803-9197-7
By: Sharma, D.; Ghosh, D.; Aziz, A.;

Measurement of Single-Event Effects on a Large Number of Commercial DRAMs

2006 / IEEE
By: Ichikawa, S.; Sasada, T.; Kanai, T.;

Interlayer coupling in ferroelectric bilayer and superlattice heterostructures

2006 / IEEE
By: Shan Zhong; Mantese, J.V.; Roytburd, A.L.; Alpay, S.P.;

A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability

2007 / IEEE
By: Hatsuda, K.; Fujita, K.; Nitayama, A.; Ohsawa, T.; Higashi, T.; Sakamoto, A.; Inoh, K.; Yamada, T.; Morikado, M.; Nakajima, H.; Kusunoki, N.; Shino, T.; Minami, Y.; Hamamoto, T.;

A Composite Circuit Model for NDR Devices in Random Access Memory Cells

2007 / IEEE
By: Akinwande, D.; Wong, H.-S.P.;

DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving

2007 / IEEE / 1-4244-1081-9
By: Zhichun Zhu; Hongzhong Zheng; Jiang Lin; David, H.; Zhao Zhang;

X-Ray Radiation Effect in DRAM Retention Time

2007 / IEEE
By: Johnston, M.; Manny Kin Ma; Ditali, A.;

Scalable Router Memory Architecture Based on Inter-leaved DRAM: Analysis and Numerical Studies

2007 / IEEE / 1-4244-0353-7
By: Feng Wang; Hamdi, M.;

Simulation of vertical channel nanoscale MOSFETs for low leakage DRAM cell

2006 / IEEE / 978-1-4244-0540-4
By: Seung-Hyun Song; Yoon-Ha Jeong; Jeong-Soo Lee;

A novel capacitor-less 2-T SOI DRAM cell

2007 / IEEE / 978-1-4244-1891-6
By: Guohe Zhang; Zhigang Hu; Zhibiao Shao;

2008 / IEEE
By: Garber, L.;

Reliability issues on the high speed DRAM flip-chip package using gold stud bump, lead free solder, and underfill

2008 / IEEE / 978-1-4244-2230-2
By: Il Whan Cho; Myoung Geun Park; Woong Sun Lee; Kwang Yoo Byun; Qwan Ho Chung; Ki Young Kim; Sung Chul Kim;

Utilizing low loss dielectric material for high performance DRAM window-BGA design

2008 / IEEE / 978-1-4244-2873-1
By: Chih-Yi Huang; Hung-Hsiang Cheng; Chih-Pin Hung; Chi-Tsung Chiu; Chen-Chao Wang;

A Dynamic Load-Balanced Hashing Scheme for Networking Applications

2008 / IEEE / 978-1-4244-2324-8
By: Artan, N.S.; Chao, H.J.; Haowei Yuan;

MBIR reflectance spectrometry for deep trench structure with ANN and Levenberg-Marquardt combined algorithm

2008 / IEEE / 978-1-4244-2176-3
By: Tielin Shi; Shiyuan Liu; Chuanwei Zhang;

Trends in radiation susceptibility of commercial DRAMs for space systems

2009 / IEEE / 978-1-4244-2621-8
By: Miller, C.; Troxel, I.A.; Schaefer, J.; Rutt, P.M.; Rose, M.; Owen, R.;

Inductively Coupled Pulsed Plasmas in the Presence of Synchronous Pulsed Substrate Bias for Robust, Reliable, and Fine Conductor Etching

2009 / IEEE
By: Jeong-Yun Lee; Junho Yoon; Collins, K.; Ramaswamy, K.; Stout, P.; Todorow, V.; Rauf, S.; Hong Cho; Tokashiki, K.; Agarwal, A.; Banna, S.; Lymberopoulos, D.; Changhun Lee; Hyun-Joong Kim; Han-Soo Cho; Sang-Jun Choi; Kyoungsub Shin;

C-Pack: A High-Performance Microprocessor Cache Compression Algorithm

2010 / IEEE
By: Dick, R.P.; Lei Yang; Xi Chen; Lekatsas, H.; Li Shang;

A Task-Centric Memory Model for Scalable Accelerator Architectures

2009 / IEEE / 978-0-7695-3771-9
By: Kelm, J.H.; Patel, S.J.; Frank, M.I.; Lumetta, S.S.; Johnson, D.R.;

Exploiting flash memory for reducing disk power consumption in portable media players

2009 / IEEE
By: Ahron Yang; Jaewoo Kim; Minseok Song;

Characterizing and mitigating the impact of process variations on phase change based memory systems

2009 / IEEE / 978-1-60558-798-1
By: Wangyuan Zhang; Tao Li;

ESKIMO - energy savings using semantic knowledge of inconsequential memory occupancy for DRAM subsystem

2009 / IEEE / 978-1-60558-798-1
By: Isen, C.; John, L.;

Memory cell capacitor using cross double patterning technology for gigabit density DRAM

2009 / IEEE / 978-1-4244-6030-4
By: Kim, K.S.; Cho, S.I.; Kim, S.G.; Cheon Bae Kim; Yong Han Roh; Lee, K.P.;

A Mechanism for Dependence of Refresh Time on Data Pattern in DRAM

2010 / IEEE
By: Myoung Jin Lee; Kun Woo Park;

A Real-Time FPGA-Based 20 000-Word Speech Recognizer With Optimized DRAM Access

2010 / IEEE
By: Wonyong Sung; Jungwook Choi; Kisun You; Young-kyu Choi;

Next Page