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Topic: Dram

Results

Prefetch-Aware Memory Controllers

2011 / IEEE
By: Mutlu, O.; Chang Joo Lee; Patt, Y.N.; Narasiman, V.;

Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM

2011 / IEEE
By: Bai-Sun Kong; Young-Hyun Jun; Dong-Su Lee;

Robust Pipelined Memory System with Worst Case Performance Guarantee for Network Processing

2012 / IEEE
By: Haiquan Zhao; Hao Wang; Jun Xu; Lin, B.;

Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap

2012 / IEEE
By: Loh, G.; Hill, M.D.;

Experimental Demonstration of Capacitorless A2RAM Cells on Silicon-on-Insulator

2012 / IEEE
By: Navarro, C.; Rodriguez, N.; Cristoloveanu, S.; Faynot, O.; Andrieu, F.; Gamiz, F.;

FlashTrie: Beyond 100-Gb/s IP Route Lookup Using Hash-Based Prefix-Compressed Trie

2012 / IEEE
By: Chao, H. J.; Lin, Y.-L.; Bando, M.;

Power management of hybrid DRAM/PRAM-based main memory

2011 / IEEE / 978-1-4503-0636-2
By: Sungjoo Yoo; Hyunsun Park; Sunggu Lee;

Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory

2011 / IEEE / 978-1-4503-0636-2
By: Xue, C.J.; Yingchao Zhao; Tiantian Liu; Minming Li;

Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies

2011 / IEEE / 978-1-4577-1056-8
By: Miclea, L.; Madalin, N.; Figueras, J.;

New reliability mechanisms in memory design for sub-22nm technologies

2011 / IEEE / 978-1-4577-1056-8
By: Canal, R.; Vatajelu, I.; Brown, A.; Asenov, A.; Aymerich, N.; Zuber, P.; Wang, X.; Vera, X.; Cheng, B.; Rubio, A.; Ramirez, T.; Pouyan, P.; Miranda, M.; Markov, S.; Herrero, E.; Gonzalez, A.; Figueras, J.;

Advanced failure analysis of memory devices

2011 / IEEE / 978-1-4577-0158-0
By: Li, S.X.;

DRAM failure cases under hot-carrier injection

2011 / IEEE / 978-1-4577-0158-0
By: ShiJie Wen; Chia, P.; Sanghyeon Baeg; Wong, R.;

A DRAM Centric NoC Architecture and Topology Design Approach

2011 / IEEE / 978-1-4577-0803-9
By: Benini, L.; Murali, S.; Seiculescu, C.; De Micheli, G.;

Exploiting Data Similarity to Reduce Memory Footprints

2011 / IEEE / 978-1-61284-372-8
By: Franklin, D.; Schulz, M.; de Supinski, B.R.; Biswas, S.; Chong, F.T.; Sherwood, T.;

Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs

2011 / IEEE / 978-1-4577-0803-9
By: Buttrick, M.; Kundu, S.;

MN-GEMS: A Timing-Aware Simulator for a Cloud Node with Manycore, DRAM, and Non-volatile Memories

2011 / IEEE / 978-1-4577-0836-7
By: Kyu Ho Park; Ki-Woong Park; Woomin Hwang;

HybridStore: A Cost-Efficient, High-Performance Storage System Combining SSDs and HDDs

2011 / IEEE / 978-1-4577-0468-0
By: Urgaonkar, B.; Gupta, A.; Youngjae Kim; Sivasubramaniam, A.; Berman, P.;

Energy efficient Phase Change Memory based main memory for future high performance systems

2011 / IEEE / 978-1-4577-1221-0
By: Beu, J.G.; Poovey, J.A.; Bheda, R.A.; Conte, T.M.;

A memory hierarchy-aware metadata management technique for Solid State Disks

2011 / IEEE / 978-1-61284-857-0
By: Kwanhu Bang; Sang-Hoon Park; Minje Jun; Eui-Young Chung;

A novel memory hierarchy with multi-channel for fast packet buffers

2011 / IEEE / 978-1-4577-0321-8
By: Zhi-Xiong Di; Kun Chen; Jiang-Yi Shi; Kang Li;

Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs

2011 / IEEE / 978-1-4577-0223-5
By: Tsuchiya, R.; Takemura, R.; Itoh, K.; Kotabe, A.; Horiguchi, M.;

A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh

2011 / IEEE / 978-1-4577-0704-9
By: Dehaene, W.; Cosemans, S.; Vignon, A.;

An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface

2011 / IEEE / 978-1-4577-0223-5
By: Mishra, N.K.; Amirkhany, A.; Sendhil, A.; Mukherjee, S.; Phuong Le; Jain, M.;

A First Analysis of a Dynamic Memory Allocation Controller (DMAC) Core

2011 / IEEE / 978-1-4577-0635-6
By: Rajasekhar, Y.; Sass, R.;

Improving PCM Endurance with Randomized Address Remapping in Hybrid Memory System

2011 / IEEE / 978-1-4577-1355-2
By: Jian Gao; Gang Wu; Yaozu Dong; Huxing Zhang;

A bursty multi-port memory controller with quality-of-service guarantees

2011 / IEEE / 978-1-4503-0715-4
By: Zefu Dai; Jianwen Zhu;

Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory

2011 / IEEE / 978-1-4577-1954-7
By: Rivers, J.A.; Kursun, E.; Guangyu Sun; Yuan Xie;

The DIMM tree architecture: A high bandwidth and scalable memory system

2011 / IEEE / 978-1-4577-1954-7
By: Reinman, G.; Ir, J.; Gyung-Su Byun; Therdsteerasukdi, K.; Chang, M.F.; Cong, J.;

The pending arrival of Phase Change Memory: The implications on the memory-storage hierarchy and on future systems development

2011 / IEEE / 978-1-4577-1617-1
By: Chiras, S.;

System implications of memory reliability in exascale computing

2011 / IEEE / 978-1-4503-0771-0
By: Sheng Li; Ke Chen; Ming-Yu Hsieh; Muralimanohar, N.; Kersey, C.D.; Brockman, J.B.; Rodrigues, A.F.; Jouppi, N.P.;

Design of static and dynamic RAM arrays using a novel reversible logic gate and decoder

2011 / IEEE / 978-1-4577-1516-7
By: Meana, R.; Lewandowski, M.; Morrison, M.; Ranganathan, N.;

Real-Time Scheduling for Phase Change Main Memory Systems

2011 / IEEE / 978-1-4577-2135-9
By: Childers, B.; Ferreira, A.P.; Bock, S.; Miao Zhou; Mosse, D.; Melhem, R.;

Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs

2011 / IEEE / 978-1-4577-1794-9
By: Mehendale, M.; Govindarajan, R.; Manikantan, R.; Gulur, N.;

Is Buffer Cache Still Effective for High Speed PCM (Phase Change Memory) Storage?

2011 / IEEE / 978-0-7695-4576-9
By: Koh, K.; Daeja Jin; Eunji Lee; Hyokyung Bahn;

A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications

2011 / IEEE / 978-1-4577-1984-4
By: Huawei Li; Yuntan Fang; Xiaowei Li;

Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments

2011 / IEEE / 978-1-4577-1794-9
By: Choudhary, D.; Hassan, S.M.; Yalamanchili, S.; Rasquinha, M.;

Phase-change memory on thin-film-transistor technology

2011 / IEEE / 978-1-4577-1756-7
By: Mansun Chan; Jin He; Lining Zhang; Lin Li;

GPEP: Graphics Processing Enhanced Pattern-Matching for High-Performance Deep Packet Inspection

2011 / IEEE / 978-1-4577-1976-9
By: Vespa, L.J.; Ning Weng;

A cellular automata based high speed test hardware for word-organized memories

2012 / IEEE / 978-1-4577-1546-4
By: Sikdar, B.K.; Saha, M.;

Bloom filter-based dynamic wear leveling for phase-change RAM

2012 / IEEE / 978-1-4577-2145-8
By: Sunggu Lee; Joosung Yun; Sungjoo Yoo;

Write-activity-aware page table management for PCM-based embedded systems

2012 / IEEE / 978-1-4673-0772-7
By: Tianzheng Wang; Chengmo Yang; Zili Shao; Duo Liu;

Near term solutions for 3D packaging of high performance DRAM

2011 / IEEE / 978-1-4577-1982-0
By: Zohni, W.; Solberg, V.;

Design and implementation of 32nm FINFET based 4� SRAM cell array using 1-bit 6T SRAM

2011 / IEEE / 978-1-4673-0074-2
By: Lourts Deepak, A.; Dhulipalla, L.;

Process variation aware DRAM design using block based adaptive body biasing algorithm

2012 / IEEE / 978-1-4673-1036-9
By: Chakraborty, K.; Roy, S.; Desai, S.;

Hybrid Memristor-CMOS memory cell: Modeling and design

2011 / IEEE / 978-1-4577-2209-7
By: Hosani, A.S.A.; Elgabra, H.; Rayahi, O.A.; Homouz, D.; Mohammad, B.;

CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory

2012 / IEEE / 978-1-4577-2145-8
By: Sheng Li; Ke Chen; Jouppi, N.P.; Brockman, J.B.; Jung Ho Ahn; Muralimanohar, N.;

The Optimization of the Hierarchical Storage System Based on the Hybrid SSD Technology

2012 / IEEE / 978-1-4577-2120-5
By: Nie Hongshan; Wang Meng; Bu Kai; Li Bo; Huang Wei;

Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier

2012 / IEEE / 978-1-4673-0438-2
By: Okobiah, O.; Garitselov, O.; Kougianos, E.; Mohanty, S.P.;

2-channel 2-layer inner-stack memory-module design for LPDDR2/3 DRAM

2012 / IEEE / 978-1-4673-1504-3
By: Jongjoo Lee; Joonhee Lee; Joon Ki Paek;

DRAM Using Crystalline Oxide Semiconductor for Access Transistors and Not Requiring Refresh for More Than Ten Days

2012 / IEEE / 978-1-4673-1081-9
By: Atsumi, T.; Yamazaki, S.; Koyama, J.; Okuda, T.; Kato, K.; Shionoiri, Y.; Inoue, H.; Isobe, A.; Okazaki, Y.; Ieda, Y.; Saito, T.; Onuki, T.; Nagatsuka, S.;

Invited tutorial: Phase Change Memory: Replacement or transformational

2012 / IEEE / 978-1-4577-1738-3
By: Lam, C.H.;

Recent developments in advanced memory modeling

2012 / IEEE / 978-1-4673-0238-8
By: Sverdlov, V.; Makarov, A.; Selberherr, S.;

Buffer-on-board memory systems

2012 / IEEE / 978-1-4673-0476-4
By: Cooper-Balis, E.; Jacob, B.; Rosenfeld, P.;

TCP reassembly for signature-based Network Intrusion Detection systems

2012 / IEEE / 978-1-4673-2025-2
By: Ngoc Thinh Tran; Tran Huy Vu; Kittitornkun, S.; Tomiyama, S.;

Modified berger codes for on-line DRAM repair strategies

2012 / IEEE / 978-1-4673-0704-8
By: Miclea, L.; Neagu, M.;

Heterogeneous multi-channel: Fine-grained DRAM control for both system performance and power efficiency

2012 / IEEE / 978-1-4503-1199-1
By: Huandong Wang; Guangfei Zhang; Peng Li; Shuai Huang; Xinke Chen;

A simple new write scheme for low latency operation of phase change memory

2012 / IEEE / 978-1-4673-0847-2
By: Chen, Y.C.; Lin, Y.Y.; Lam, C.; Lung, H.L.; BrightSky, M.; Lee, F.M.;

Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes

2012 / IEEE / 978-1-4673-1605-7
By: Franchetti, F.; Milder, P.A.; Akin, B.; Hoe, J.C.;

Transpose-free SAR imaging on FPGA platform

2012 / IEEE / 978-1-4673-0219-7
By: Chakrabarti, Chaitali; Yu, Chi-Li;

A 30 Gb/s/Link 2.2 Tb/s/mm $^{2}$ Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface

2011 / IEEE
By: Kuroda, T.; Miura, N.; Take, Y.;

Low-Power 10-Gb/s Transmitter for High-Speed Graphic DRAMs Using 0.18- $\mu\hbox{m}$ CMOS Technology

2011 / IEEE
By: Jun-Yong Song; Oh-Kyong Kwon;

$\hbox{Ge}_{2}\hbox{Sb}_{2}\hbox{Te}_{5}$ as a Ferroelectric: A Single-Element Low-Voltage Dynamic Memory

2012 / IEEE
By: Sang Hyeon Lee; Moonkyung Kim; Byung-ki Cheong; Jo-Won Lee; Tiwari, S.;

A 0.5 V Operation $V _{\rm TH}$ Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems

2011 / IEEE
By: Takeuchi, K.; Tanakamaru, S.;

A 1 TB/s 1 pJ/b 6.4 ${\rm mm}^{2}/{\rm TB/s}$ QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM

2012 / IEEE
By: Miura, N.; Kuroda, T.; Saito, M.;

Welcome to the Entropics: Boot-Time Entropy in Embedded Devices

2013 / IEEE
By: Mowery, Keaton; Swanson, Steven; Shacham, Hovav; Kohlbrenner, David; Wei, Michael;

Recent advances in memory technology

2013 / IEEE
By: James, Dick;

Non-volatile FPGAs based on spintronic devices

2013 / IEEE
By: Goncalves, Olivier; Dieny, Bernard; Di Pendina, Gregory; Prenat, Guillaume;

Vref optimization in DDR4 RDIMMs for improved timing margins

2014 / IEEE
By: Kim, Kyu-Hyoun; Saurabh, Abhijit; Wright, Kenneth; Lingambudi, Anil; Sethuraman, Saravanan; Becker, Dale;

A high-retention 2T embedded DRAM with cell-body toggle scheme

2014 / IEEE
By: Zheng, Huarong; Chung, Yeonbae; Cheng, Weijie; Zhou, Baolong;

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

2014 / IEEE
By: Lin, Wei; Faltermeier, Johnathan; Iyer, Subramanian; Berger, Dan; McHerron, Dale; Canaperi, Donald; Wynne, Jean; Demarest, James J; Winstel, Kevin; Skordas, Spyridon; Graves-Abe, Troy; Batra, Pooja; Herman, Kenneth; Golz, John; Kirihata, Toshiaki; Garant, John; Hubbard, Alex; Cauffman, Kris; Levine, Theodore; Kelly, James; Priyadarshini, Deepika; Peethala, Brown; Patlolla, Raghuveer; Shoudy, Matthew;

Enhancement of DRAMs performance using resonant tunneling diode buffer

2014 / IEEE
By: Elgreatly, Ahmed Lutfi; El-Rabaie, El-Sayed M.; Shaaban, Ahmed Ahmed;

Energy-efficient histogram equalization on FPGA

2014 / IEEE
By: Sanny, Andrea; Prasanna, Viktor K.; Yang, Yi-Hua E.;

Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories

2015 / IEEE
By: Meinerzhagen, Pascal; Giterman, Robert; Karakonstantis, Georgios; Teman, Adam; Burg, Andreas;

Reduction of Leakage Power & Noise for DRAM Design Using Sleep Transistor Technique

2015 / IEEE
By: Saxena, Nikhil; Kushwah, Priyanka; Saurabh; Akashe, Shyam;

RBPP: A row based DRAM page policy for the many-core era

2014 / IEEE
By: Song, Fenglong; Shen, Xiaowei; Zhang, Zhimin; An, Shuqian; Meng, Haibo;

Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures

2014 / IEEE
By: Nair, Prashant J.; Qureshi, Moinuddin K.; Roberts, David A.;

BuMP: Bulk Memory Access Prediction and Streaming

2014 / IEEE
By: Falsafi, Babak; Picorel, Javier; Volos, Stavros; Grot, Boris;

Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth

2014 / IEEE
By: Gulur, Nagendra; Govindarajan, R.; Manikantan, R.; Mehendale, Mahesh;

Low Overhead Software Wear Leveling for Hybrid PCM + DRAM Main Memory on Embedded Systems

2015 / IEEE
By: Xie, M.; Hu, J.; Sha, E.H.; Zhuge, Q.; Xue, C.J.; Pan, C.;

Opportunities for Nonvolatile Memory Systems in Extreme-Scale High-Performance Computing

2015 / IEEE
By: Mittal, Sparsh; Vetter, Jeffrey S.;

Memory Die Clustering and Matching for Optimal Voltage Window in Semiconductor

2015 / IEEE
By: Kang, S.; Park, Y.; Cho, S.;

1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design

2015 / IEEE
By: Biswas, A.; Ionescu, A.M.;

Investigation of intermediate dielectric for dual floating gate MOSFET

2013 / IEEE
By: Lee, Bongmook; Di Spigna, Neil; Jayanti, Srikant; Sarkar, Biplab; Franzon, Paul; Misra, Veena;

Ultra fast, two-bit ECC for Emerging Memories

2014 / IEEE
By: Bellini, S.; Sforzin, M.; Laurent, C.; Amato, P.; Tomasoni, A.; Ferrari, M.;

Thermal stability and reliability in SiGe pMOSFETs for sub-20nm DRAM applications

2014 / IEEE
By: Noh, Kyung Bong; Son, Yunik; Thean, Aaron; Horiguchi, Naoto; Franco, Jacopo; Aoulaiche, Marc; Fazan, Pierre; Spessot, Alessio; Schram, Tom; Ritzenthaler, Romain; Cho, Moonju;

Optimizated Allocation of Data Variables to PCM/DRAM-based Hybrid Main Memory for Real-Time Embedded Systems

2014 / IEEE
By: Shao, Z.; Gu, Z.; Wang, Z.;

Maximizing DRAM performance using selective operating frequency boosting

2014 / IEEE
By: Jung, Jung Ho; Ro, Won Woo; Lee, Changmin; Kim, Seung Hun;

Impact of FinFET and III–V/Ge Technology on Logic and Memory Cell Behavior

2014 / IEEE
By: Rubio, A.; Canal, R.; Aymerich, N.; Almudever, C. G.; Calomarde, A.; Amat, E.;

Optimal page allocation approach on the hybrid DRAM/PCRAM memory architecture

2014 / IEEE
By: Yang, Jhih-Kai; Cheng, Wei-Kai;

The Xbox One System on a Chip and Kinect Sensor

2014 / IEEE
By: O'Connor, Patrick; Sell, John;

A memory schedule policy oriented to stream architecture

2014 / IEEE
By: Ma Chiyuan; Ni Xiaoqiang;

Leakage Control in 0.4-nm EOT Ru/SrTiOx/Ru Metal-Insulator-Metal Capacitors: Process Implications

2014 / IEEE
By: Jurczak, M.; Van Elshocht, S.; Hody, H.; Olk, C.; Jourdan, N.; Afanasev, V.V.; Swerts, J.; Caillat, C.; Clima, S.; Redolfi, A.; Aoulaiche, M.; Kaczer, B.; Popovici, M.; Wang, W.C.;

What the Future Holds for Solid-State Memory

2014 / IEEE
By: Strauss, Karin; Burger, Doug;

Characterizing Application Memory Error Vulnerability to Optimize Datacenter Cost via Heterogeneous-Reliability Memory

2014 / IEEE
By: Liu, Jie; Kansal, Aman; Meza, Justin; Santaniello, Mark; Khessib, Badriddine; Govindan, Sriram; Luo, Yixin; Mutlu, Onur; Vaid, Kushagra; Sharma, Bikash;

Improving power efficiency of GPGPU's global memory by a hybrid memory approach

2014 / IEEE
By: Yu, Zhibin; Chen, Kai; Li, Xiaoke; Liu, Jin; Xu, Chengzhong;

Microstructure processing and micromagnetic simulations of magnetic tunnel junction based low power magnetic memories

2014 / IEEE
By: Chakraverty, Mayank; Kittur, Harish M;

Re-using Refresh for Self-Testing DRAMs

2013 / IEEE
By: Sengupta, Indranil; Mandal, Chittaranjan; Ghoshal, Bibhas;

Application Aware DRAM Bank Partitioning in CMP

2013 / IEEE
By: Ikeda, Takakazu; Kise, Kenji;

A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches

2014 / IEEE
By: O'Connor, Mike; Sridharan, Vilas; Loh, Gabriel H.; Sim, Jaewoong;

Mini-Rank: A Power-EfficientDDRx DRAM Memory Architecture

2014 / IEEE
By: Fang, K.; Zhu, Z.; Zhang, Z.; Lin, J.; Zheng, H.;

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