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Topic: Dram Chips

Results

Highly Manufacturable Device Isolation Technology Using Laser-Induced Epitaxial Growth for Monolithic Stack Devices
2011 / IEEE
By: Seung Jae Baik; Yong-Hoon Son; Euijoon Yoon; Yoo Gyun Shin; Gihyun Hwang; Jong-Wook Lee; Sanghun Jeon;
Prefetch-Aware Memory Controllers
2011 / IEEE
By: Mutlu, O.; Chang Joo Lee; Patt, Y.N.; Narasiman, V.;
Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances
2011 / IEEE
By: Roy, K.; De, V.; Tschanz, J.; Somasekhar, D.; Raychowdhury, A.; Augustine, C.;
Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM
2011 / IEEE
By: Bai-Sun Kong; Young-Hyun Jun; Dong-Su Lee;
Application-Aware NoC Design for Efficient SDRAM Access
2011 / IEEE
By: Pan, D.Z.; Wooyoung Jang;
A Novel 1T-1D DRAM Cell for Embedded Application
2012 / IEEE
By: Cheng-Wei Cao; Zhang, D.W.; Peng-Fei Wang; Xing, C.; Qing-Qing Sun; Xi Lin; Song-Gan Zang;
Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management
2012 / IEEE
By: Mutlu, O.; HanBin Yoon; Jichuan Chang; Meza, J.; Ranganathan, P.;
Robust Pipelined Memory System with Worst Case Performance Guarantee for Network Processing
2012 / IEEE
By: Haiquan Zhao; Hao Wang; Jun Xu; Lin, B.;
A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor
2012 / IEEE
By: Jain, P.; Wei Zhang; Ki Chul Chun; Kim, C.H.;
Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap
2012 / IEEE
By: Loh, G.; Hill, M.D.;
A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches
2012 / IEEE
By: Jain, P.; Ki Chul Chun; Kim, C.H.; Tae-Ho Kim;
A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface
2012 / IEEE
By: Amirkhany, A.; Xingchao Yuan; Mishra, N.K.; Jie Shen; Beyene, W.T.; Chen, C.; Chin, T.J.; Dressier, D.; Huang, C.; Gadde, V.P.; Hekmat, M.; Kaviani, K.; Hai Lan; Phuong Le; Mahabaleshwara; Madden, C.; Mukherjee, S.; Raghavan, L.; Saito, K.; Secker, D.; Sendhil, A.; Schmitt, R.; Fazeel, S.; Srinivas, G.S.; Ting Wu; Chanh Tran; Vaidyanath, A.; Vyas, K.; Ling Yang; Jain, M.; Chang, K.-Y.K.; Wei, J.;
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface
2012 / IEEE
By: Kaviani, K.; Xingchao Yuan; Wei, J.; Amirkhany, A.; Jie Shen; Chin, T.J.; Thakkar, C.; Beyene, W.T.; Chan, N.; Chen, C.; Bing Ren Chuang; Dressler, D.; Gadde, V.P.; Hekmat, M.; Ho, E.; Huang, C.; Phuong Le; Mahabaleshwara; Madden, C.; Mishra, N.K.; Raghavan, L.; Saito, K.; Schmitt, R.; Secker, D.; Xudong Shi; Fazeel, S.; Srinivas, G.S.; Zhang, S.; Tran, C.; Vaidyanath, A.; Vyas, K.; Jain, M.; Kun-Yung Ken Chang; Ting Wu;
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces
2012 / IEEE
By: Hyun-Woo Lee; Byong-Tae Chung; Beom-Ju Shin; Kyung-Hoon Kim; Kyung-Whan Kim; Jaeil Kim; Kwang-Hyun Kim; Jong-Ho Jung; Jae-Hwan Kim; Eun-Young Park; Jong-Sam Kim; Jong-Hwan Kim; Jin-Hee Cho; Namgyu Rye; Jun-Hyun Chun; Yunsaing Kim; Chulwoo Kim; Young-Jung Choi; Hoon Choi;
Carrier Lifetime Engineering for Floating-Body Cell Memory
2012 / IEEE
By: Sung-Jin Choi; Sungho Kim; Yang-Kyu Choi; Dong-Il Moon;
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology
2012 / IEEE
By: Byong-Tae Chung; Young-Jung Choi; Chulwoo Kim; Kwan-Weon Kim; Hyun-Woo Lee; Ju-Hwan Sohn; Young-Kyoung Choi; Ki-Han Kim; Nak-Kyu Park;
Characteristics of a Smiling Polysilicon Thin-Film Transistor
2012 / IEEE
By: Po-Hsieh Lin; Yi-Chuen Eng; Tzu-Feng Chang; Jyi-Tsong Lin; Cheng-Hsin Chen;
Experimental Demonstration of Capacitorless A2RAM Cells on Silicon-on-Insulator
2012 / IEEE
By: Navarro, C.; Rodriguez, N.; Cristoloveanu, S.; Faynot, O.; Andrieu, F.; Gamiz, F.;
A BJT-Based Heterostructure 1T-DRAM for Low-Voltage Operation
2012 / IEEE
By: In-Young Chung; Kyung-Suk Shim; Park, Y.J.;
Variation Study and Implications for BJT-Based Thin-Body Capacitorless DRAM
2012 / IEEE
By: Min Hee Cho; Tsu-Jae King Liu;
Hybrid partitioned H.264 full high definition decoder on embedded quad-core
2012 / IEEE
By: Shihwa Lee; Do-Hyung Kim; Joon Ho Song; Minsoo Kim;
Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories
2012 / IEEE
By: Jing Chen; Qingqing Wu; Fossum, J.G.; Xi Wang; Pang, A.; Zhenming Zhou; Zhichao Lu; Chao Qiu; Tao Yu; Zhan Chai; Jiexin Luo; Le Li;
Dependence of DRAM Device Performance on Passivation Annealing Position in Trench and Stack Structures for Manufacturing Optimization
2012 / IEEE
By: Wang, D. H.-L.; Yang, C.-M.; Lai, C.-S.; Lee, C.-Y.;
Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System
2012 / IEEE
By: Gyung-Su Byun; Therdsteerasukdi, K.; Chang, M.F.; Cong, J.; Reinman, G.; Ir, J.;
DRAM Data Retention and Cell Transistor Threshold Voltage Reliability Improved by Passivation Annealing Prior to the Deposition of Plasma Nitride Layer
2012 / IEEE
By: Wang, D.H.-L.; Chia-Ming Yang; Chao-Sung Lai; Chung-Yuan Lee;
Impact of Cu Contamination on Memory Retention Characteristics in Thinned DRAM Chip for 3-D Integration
2012 / IEEE
By: Fukushima, T.; Ohara, Y.; Naganuma, H.; Tani, T.; Kangwook Lee; Koyanagi, M.; Tanaka, T.;
Power Variability in Contemporary DRAMs
2012 / IEEE
By: Gupta, P.; Kagalwalla, A.A.; Gottscho, M.;
A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration
2012 / IEEE
By: Cristoloveanu, S.; Zaslavsky, A.; Le Royer, C.; Wan, J.;
Performance Improvement of One-Transistor DRAM by Band Engineering
2012 / IEEE
By: Gupta, S.; Nainani, A.; Pal, A.; Saraswat, K.C.;
Floating Body Effect in Partially Depleted Silicon Nanowire Transistors and Potential Capacitor-Less One-Transistor DRAM Applications
2012 / IEEE
By: Taeho Moon; Myeongwon Lee; Sangsig Kim;
Reducing DRAM Image Data Access Energy Consumption in Video Processing
2012 / IEEE
By: Tong Zhang; Yiran Li;
Low-Power Time Deinterleaver for ISDB-T Receiver
2012 / IEEE
By: Hyeong-Ju Kang; Byung-Do Yang;
Testing Methodology of Embedded DRAMs
2012 / IEEE
By: Hao-Yu Yang; Shih-Chin Lin; Rei-Fu Huang; Chao, M.C.; Chi-Min Chang;
An approach to single event testing of SDRAMs
2009 / IEEE / 978-1-4577-0493-2
By: McPeak, R.; Edmonds, L.; Adell, P.C.; McClure, S.S.; Scheick, L.;
Ultra-low leakage junction engineering of cell transistor by raised source/drain for logic-compatible 28-nm embedded DRAM
2011 / IEEE / 978-1-4244-9949-6
By: Uejima, K.; Hase, T.;
3D stackable 32nm High-K/Metal Gate SOI embedded DRAM prototype
2011 / IEEE / 978-1-61284-175-5
By: Bishan He; Fainstein, D.; Safran, J.; Golz, J.; Iyer, S.; Ken Rim; Kirihata, T.; Robson, N.; Barth, J.; Leu, D.; Kothandaraman, C.; Maier, G.; Himmel, B.; Cestero, A.; Yan Sun; Vehabovic, A.; Weaver, T.; Ming Yin;
High-performance on-chip network platform for memory-on-processor architectures
2011 / IEEE / 978-1-4577-0642-4
By: Daneshtalab, M.; Tenhunen, H.; Plosila, J.; Liljeberg, P.; Ebrahimi, M.;
A tri-modal 20Gbps/link differential/DDR3/GDDR5 memory interface
2011 / IEEE / 978-1-61284-175-5
By: Amirkhany, A.; Secker, D.; Wu, T.; Kaviani, K.; Yuan, C.; Chang, K.; Jain, M.; Vyas, K.; Vaidyanath, A.; Tran, C.; Srinivas, S.; Shuaeb, F.; Shi, X.; Wei, J.; Saito, K.; Raghavan, L.; Mishra, N.; Madden, C.; M, M.; Le, P.; Huang, C.; Gadde, V.; Dressler, D.; Beyene, W.; Chin, T.; Chen, C.; Shen, J.;
High-PSRR all-digital delay locked loop with burst update mode and power noise damping scheme
2011 / IEEE / 978-1-61284-175-5
By: Yongju Kim; Jaemin Jang; Jinyeong Moon; Seongjun Lee; Daehan Kwon; Hongseok Choi; Geunwoo Park; Byongtae Chung;
A 12.8-Gb/s/link tri-modal single-ended memory interface for graphics applications
2011 / IEEE / 978-1-61284-175-5
By: Amirkhany, A.; Wei, J.; Yuan, C.; Chang, K.; Jain, M.; Vyas, K.; Vaidyanathan, A.; Tran, C.; Wu, T.; Srinivas, S.; Shuaeb, F.; Secker, D.; Saito, K.; Raghavan, L.; Mukherjee, S.; Madden, C.; M, M.; Le, P.; Kaviani, K.; Gadde, V.; Huang, C.; Chin, T.; Beyene, W.; Shen, J.; Mishra, N.;
Power management of hybrid DRAM/PRAM-based main memory
2011 / IEEE / 978-1-4503-0636-2
By: Sungjoo Yoo; Hyunsun Park; Sunggu Lee;
Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory
2011 / IEEE / 978-1-4503-0636-2
By: Xue, C.J.; Yingchao Zhao; Tiantian Liu; Minming Li;
Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies
2011 / IEEE / 978-1-4577-1056-8
By: Miclea, L.; Madalin, N.; Figueras, J.;
Offset buried metal gate vertical floating body memory technology with excellent retention time for DRAM application
2011 / IEEE / 978-1-4244-9949-6
By: Banna, S.; Tang, C.; Sang-Min Hwang; Hong, S.-J.; Van Buskirk, M.; Lee, J.-H.; Roh, J.-S.; Cho, S.-H.; Sung-Woong Chung; Park, J.-W.; Chung, S.-J.; Lee, J.-Y.; Seung-Hwan Lee; Joong-Sik Kim; Jungtae Kwon; Kim, D.; Thurgate, T.; Gupta, M.; Bhardwaj, S.;
FPGA realization of multi-port SDRAM controller in real time image acquisition system
2011 / IEEE / 978-1-61284-774-0
By: Dechun Zheng; Ying Zhang; Yang Yang;
Advanced failure analysis of memory devices
2011 / IEEE / 978-1-4577-0158-0
By: Li, S.X.;
Stress induced self aligned contact failure during tungsten-poly gate process in sub-60 nm memory device
2011 / IEEE / 978-1-4577-0158-0
By: Min-Gyu Sung; Sung-Ki Park; Yong Soo Kim;
The properties comparison between Au and Cu wires bond in DRAM component
2011 / IEEE / 978-1-4577-0158-0
By: Tseng, C.E.; Meiying Hsiao; Yi Heang Chen;
DRAM failure cases under hot-carrier injection
2011 / IEEE / 978-1-4577-0158-0
By: ShiJie Wen; Chia, P.; Sanghyeon Baeg; Wong, R.;
A DRAM Centric NoC Architecture and Topology Design Approach
2011 / IEEE / 978-1-4577-0803-9
By: Benini, L.; Murali, S.; Seiculescu, C.; De Micheli, G.;
Exploiting Data Similarity to Reduce Memory Footprints
2011 / IEEE / 978-1-61284-372-8
By: Franklin, D.; Schulz, M.; de Supinski, B.R.; Biswas, S.; Chong, F.T.; Sherwood, T.;
MN-GEMS: A Timing-Aware Simulator for a Cloud Node with Manycore, DRAM, and Non-volatile Memories
2011 / IEEE / 978-1-4577-0836-7
By: Kyu Ho Park; Ki-Woong Park; Woomin Hwang;
Characterizing Memory Write References for Efficient Management of Hybrid PCM and DRAM Memory
2011 / IEEE / 978-1-4577-0468-0
By: Soyoon Lee; Noh, S.H.; Hyokyung Bahn;
HybridStore: A Cost-Efficient, High-Performance Storage System Combining SSDs and HDDs
2011 / IEEE / 978-1-4577-0468-0
By: Urgaonkar, B.; Gupta, A.; Youngjae Kim; Sivasubramaniam, A.; Berman, P.;
Exploring performance, power, and temperature characteristics of 3D systems with on-chip DRAM
2011 / IEEE / 978-1-4577-1221-0
By: Rossell, D.; Jie Meng; Coskun, A.K.;
Energy efficient Phase Change Memory based main memory for future high performance systems
2011 / IEEE / 978-1-4577-1221-0
By: Beu, J.G.; Poovey, J.A.; Bheda, R.A.; Conte, T.M.;
Automatic Generation of Efficient Predictable Memory Patterns
2011 / IEEE / 978-1-4577-1118-3
By: Hayes, W.; Akesson, B.; Goossens, K.;
Memory Access Aware Mapping for Networks-on-Chip
2011 / IEEE / 978-1-4577-1118-3
By: Nan Guan; Xi Jin; Wang Yi; Qingxu Deng;
Leveraging on-chip DRAM stacking in an embedded 3D multi-core DSP system
2011 / IEEE / 978-1-61284-857-0
By: Tingting Hwang; Jen-Chieh Yeh; Chuan-Nan Liu; Yi-Ta Wu; Yuan Xie; Shau-Yin Tseng; Wei-Heng Lo; Po-Yang Hsu; Tao Zhang;
Optical burst switching for many-core processor-to-memory photonic networks
2011 / IEEE / 978-1-4244-9718-8
By: Huanzhong Li; Dongson Ban; Quanyou Feng; Wenhua Dou;
3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption
2011 / IEEE / 978-1-61284-857-0
By: Inoue, K.; Murakami, K.; Fukumoto, N.; Ueno, S.; Hashiguchi, S.;
A memory hierarchy-aware metadata management technique for Solid State Disks
2011 / IEEE / 978-1-61284-857-0
By: Kwanhu Bang; Sang-Hoon Park; Minje Jun; Eui-Young Chung;
A scalable I/O architecture for wide I/O DRAM
2011 / IEEE / 978-1-61284-857-0
By: Harvard, Q.; Baker, R.J.;
Exploring energy-efficient DRAM array organizations
2011 / IEEE / 978-1-61284-857-0
By: Seongil, O.; Jung Ho Ahn; Sungwoo Choo;
Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs
2011 / IEEE / 978-1-4577-0223-5
By: Tsuchiya, R.; Takemura, R.; Itoh, K.; Kotabe, A.; Horiguchi, M.;
An design of FPGA based high definition image real-time recorder on demand
2011 / IEEE / 978-1-4577-0321-8
By: Yiqing Liu; Xining Yu;
Design of embedded media player based on S3C2440 and SDL_FFMPEG
2011 / IEEE / 978-1-4244-8165-1
By: Mingyu Gao; Wenhao Wang;
Novel 4F2 DRAM cell with Vertical Pillar Transistor(VPT)
2011 / IEEE / 978-1-4577-0708-7
By: Yong Chul Oh; Jiyoung Kim; Ki-Whan Song; Hyungi Kim; Sua Kim; Kanguk Kim; Yoosang Hwang; Huijung Kim; Hyunwoo Chung; Chilhee Chung; Gyo-Young Jin; Hyeongsun Hong;
A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh
2011 / IEEE / 978-1-4577-0704-9
By: Dehaene, W.; Cosemans, S.; Vignon, A.;
An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface
2011 / IEEE / 978-1-4577-0223-5
By: Mishra, N.K.; Amirkhany, A.; Sendhil, A.; Mukherjee, S.; Phuong Le; Jain, M.;
A First Analysis of a Dynamic Memory Allocation Controller (DMAC) Core
2011 / IEEE / 978-1-4577-0635-6
By: Rajasekhar, Y.; Sass, R.;
Improving PCM Endurance with Randomized Address Remapping in Hybrid Memory System
2011 / IEEE / 978-1-4577-1355-2
By: Jian Gao; Gang Wu; Yaozu Dong; Huxing Zhang;
Memory controllers for high-performance and real-time MPSoCs requirements, architectures, and future trends
2011 / IEEE / 978-1-4503-0715-4
By: Tei-Wei Kuo; Yuan-Hao Chang; Goossens, K.; Dutoit, D.; Vivet, P.; Clermidy, F.; Po-Chun Huang; Akesson, B.; Wingard, D.;
A bursty multi-port memory controller with quality-of-service guarantees
2011 / IEEE / 978-1-4503-0715-4
By: Zefu Dai; Jianwen Zhu;
SEEs Induced by High-Energy Protons and Neutrons in SDRAM
2010 / IEEE / 978-1-4577-1281-4
By: Graham, P.; Quinn, H.; Fairbanks, T.;
PRET DRAM controller: Bank privatization for predictability and temporal isolation
2011 / IEEE / 978-1-4503-0715-4
By: Liu, I.; Reineke, J.; Lee, E.A.; Sungjun Kim; Patel, H.D.;
10 Gb/s, 1� optical link for DRAM interconnect
2011 / IEEE / 978-1-4244-8340-2
By: Lee, B.S.; Byun, H.I.; Park, Y.D.; Chung, C.H.; Ha, K.H.; Hong, S.Y.; Choi, Y.; Shin, Y.H.; Suh, S.D.; Joe, I.S.; Kim, S.G.; Cho, K.S.; Na, K.W.; Ji, H.-C.; Lee, K.-H.; Shin, D.J.; Pyo, J.;
Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory
2011 / IEEE / 978-1-4577-1954-7
By: Rivers, J.A.; Kursun, E.; Guangyu Sun; Yuan Xie;
An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems
2011 / IEEE / 978-1-4577-1954-7
By: Nicopoulos, C.; Seungcheol Baek; Hyung Gyu Lee; Jongman Kim;
The DIMM tree architecture: A high bandwidth and scalable memory system
2011 / IEEE / 978-1-4577-1954-7
By: Reinman, G.; Ir, J.; Gyung-Su Byun; Therdsteerasukdi, K.; Chang, M.F.; Cong, J.;
Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors
2011 / IEEE / 978-1-4577-1954-7
By: Canal, R.; Ganapathy, S.; Rubio, A.; Gonzalez, A.;
Plane bounce in high-speed single-ended signaling I/O interfaces
2011 / IEEE / 978-1-4244-9401-9
By: Oh, D.;
Reconfigurable cache memory architecture for integral image and integral histogram applications
2011 / IEEE / 978-1-4577-1921-9
By: Po-Hao Hsu; Shao-Yi Chien;
1T-DRAM at the 22nm technology node and beyond: An alternative to DRAM with high-k storage capacitor
2011 / IEEE / 978-1-4577-1025-4
By: Martinez, F.; Sagnes, B.; Chang, S.J.; Hubert, A.; Guegan, G.; Pascal, F.; Cristoloveanu, S.; Bawedin, M.; Hoffmann, A.; Valenza, M.;
Novel memory ideas using floating body effects
2011 / IEEE / 978-1-61284-760-3
By: Jin Cho;
BJT effect analysis in p- and n-SOI MuGFETs with high-k gate dielectrics and TiN metal gate electrode for a 1T-DRAM application
2011 / IEEE / 978-1-61284-760-3
By: Claeys, C.; Jurczak, M.; Aoulaiche, M.; Simoen, E.; Galeti, M.; Martino, J.A.; Rodrigues, M.; Collaert, N.;
High density DRAM for space utilizing embedded DRAMs macros in 32nm SOI CMOS
2011 / IEEE / 978-1-61284-760-3
By: Popp, J.; Braatz, J.; McKay, T.; Rabaa, S.; Ballast, J.;
The pending arrival of Phase Change Memory: The implications on the memory-storage hierarchy and on future systems development
2011 / IEEE / 978-1-4577-1617-1
By: Chiras, S.;
Bandwidth-aware reconfigurable cache design with hybrid memory technologies
2011 / IEEE / 978-1-4577-1400-9
By: Jishen Zhao; Yuan Xie; Cong Xu;
New methods and tools for design of tests memory
2011 / IEEE / 978-1-4577-1958-5
By: Ryabtsev, V.; Moamar, D.; Almadi, M.;
Variable and clause elimination in SAT problems using an FPGA
2011 / IEEE / 978-1-4577-1740-6
By: Maruyama, T.; Suzuki, M.;
Design of static and dynamic RAM arrays using a novel reversible logic gate and decoder
2011 / IEEE / 978-1-4577-1516-7
By: Meana, R.; Lewandowski, M.; Morrison, M.; Ranganathan, N.;
CARMEN-2: In flight observation of non destructive single event phenomena on memories
2011 / IEEE / 978-1-4577-0586-1
By: Bezerra, F.; Samaras, A.; Ecoffet, R.; Lorfevre, E.;
Unified extensible firmware interface: An innovative approach to DRAM power control
2011 / IEEE / 978-1-4673-0465-8
By: Khanna, R.; Kumar, M.J.; Le, C.; Nachimuthu, M.; Zuhayri, F.;
Heavy ion SEE test of 2 Gbit DDR3 SDRAM
2011 / IEEE / 978-1-4577-0586-1
By: Grurmann, K.; Herrmann, M.; Ferlet-Cavrois, V.; Kettunen, H.; Gliem, F.;
A Hardware/Software Countermeasure and a Testing Framework for Cache Based Side Channel Attacks
2011 / IEEE / 978-1-4577-2135-9
By: Jayasinghe, D.; Ragel, R.; Parameswaran, S.; Arora, A.;
Characterization of SEFI events on the EDODRAM used in large space solid state memory
2011 / IEEE / 978-1-4577-0586-1
By: Lochon, F.; Grandjean, M.; Mazurek, M.; Damery, J.C.; Dangla, D.; Standarovski, D.; Guerre, F.X.;
Investigations of single event effects with heavy ions of energies up to 1.5 GeV/n
2011 / IEEE / 978-1-4577-0586-1
By: Harboe-Sorensen, R.; Pleskac, R.; Ferlet-Cavrois, V.; Durante, M.; Hoeffgen, S.K.; Weinand, U.; Schardt, D.; Poivey, C.; Lennartz, W.; Nieminen, P.; Metzger, S.; Menicucci, A.; Mathes, M.; LaTessa, C.; Kuhnhenn, J.; Kuendgen, T.;
Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs
2011 / IEEE / 978-1-4577-1794-9
By: Mehendale, M.; Govindarajan, R.; Manikantan, R.; Gulur, N.;
Impact of GND-PTH stitches in DDR3/GDDR3/GDDR5 Memory controller packages
2011 / IEEE / 978-95-318-4158-0
By: Badesha, A.; Ahmad, H.;

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