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A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

By: Seo, K. -I.; Haran, B.; Gupta, D.; Guo, D.; Standaert, T.; Xie, R.; Shang, H.; Alptekin, E.; Bae, D. -I.; Bae, G.; Boye, C.; Cai, H.; Chanemougame, D.; Chao, R.; Cheng, K.; Cho, J.; Choi, K.; Hamieh, B.; Hong, J. G.; Hook, T.; Jang, L.; Jung, J.; Jung, R.; Lee, D.; Lherron, B.; Kambhampati, R.; Kim, B.; Kim, H.; Kim, K.; Kim, T. S.; Ko, S.-B.; Lie, F. L.; Liu, D.; Mallela, H.; Mclellan, E.; Mehta, S.; Montanini, P.; Mottura, M.; Nam, J.; Nam, S.; Nelson, F.; Ok, I.; Park, C.; Park, Y.; Paul, A.; Prindle, C.; Ramachandran, R.; Sankarapandian, M.; Sardesai, V.; Scholze, A.; Seo, S. -C; Shearer, J.; Southwick, R.; Sreenivasan, R.; Stieg, S.; Strane, J.; Sun, X.; Sung, M. G.; Surisetty, C.; Tsutsui, G.; Tripathi, N.; Vega, R.; Waskiewicz, C.; Weybright, M.; Yeh, C.-C.; Bu, H.; Burns, S.; Canaperi, D.; Celik, M.; Colburn, M.; Jagannathan, H.; Kanakasabaphthy, S.; Kleemeier, W.; Liebmann, L.; Mcherron, D.; Oldiges, P.; Paruchuri, V.; Spooner, T.; Stathis, J.; Divakaruni, R.; Gow, T.; Iacoponi, J.; Jenq, J.; Sampson, R.; Khare, M.;

2014 / IEEE

Description

This item from - IEEE Conference - 2014 IEEE Symposium on VLSI Technology - A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.