Your Search Results

Use this resource - and many more! - in your textbook!

AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

Device-level PBTI-induced timing jitter increase in circuit-speed random logic operation

By: Lu, J.W.; Vaz, C.; Young, C.D.; Bersuker, G.; Jiao, G.F.; Cheung, K.P.; Ryan, J.T.; Campbell, J.P.;

2014 / IEEE

Description

This item from - IEEE Conference - 2014 IEEE Symposium on VLSI Technology - We utilize eye-diagram measurements of timing jitter to investigate the impact of PBTI in devices subject to DC as well as ring oscillator (RO) and pseudo-random binary sequence (PRBS) stress waveforms. We observe that RO measurements miss the relevant random timing jitter increases which are well captured using PRBS measurements. We also observe that DC, RO, and PRBS stresses all introduce similar increases in random timing jitter. This calls into question the widely assumed degradation headroom between DC and AC measurements. This work collectively provides a snapshot of PBTI degradation in “real” circuit environments. It provides a path for more accurate and realistic circuit lifetime estimations and circuit timing budget criteria.