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A 65-nm CMOS 10-GS/s 4-bit Background-Calibrated Noninterleaved Flash ADC for Radio Astronomy
By: Belostotski, L.; Xu, Y.; Haslett, J.W.;
2014 / IEEE
This item from - IEEE Transaction - Components, Circuits, Devices and Systems - This paper presents a 4-bit noninterleaved single-clock-phase 10-GS/s analog-to-digital converter (ADC) fabricated in TSMC 65-nm CMOS technology. The ADC is realized using novel switched dynamic comparators (SDCs), which alleviate the clock-frequency-limiting long regeneration time in prior-art dynamic comparators, and avoid the phase-skew issue associated with time-interleaved ADCs that limits their signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range. The SDC employs a reference-free topology and has no static power consumption. The trip voltage errors of the SDCs are corrected by an efficient on-chip digital background calibration technique. The noninterleaved ADC presents an estimated 100 fF of capacitance at its input, excluding bondpad capacitance, with most of it contributed by the traces leading to the ADC and the shielding structures associated with the input traces. At 10-GS/s sampling rate, the prototype ADC achieves an SNDR of 24.9 dB [3.84 effective number of bit (ENOB)], and 23.4 dB (3.59 ENOB) at low input signal frequencies and Nyquist, respectively. The chip consumes 104 mW from a 1.3 V supply. The ADC has an active area of 0.1