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10nm FINFET technology for low power and high performance applications

By: Guo, D.; Shang, H.; Seo, K.; Haran, B.; Standaert, T.; Gupta, D.; Alptekin, E.; Bae, D.; Bae, G.; Chanemougame, D.; Cheng, K.; Cho, J.; Hamieh, B.; Hong, J.; Hook, T.; Jung, J.; Kambhampati, R.; Kim, B.; Kim, H.; Kim, K.; Kim, T.; Liu, D.; Mallela, H.; Montanini, P.; Mottura, M.; Nam, S.; Ok, I.; Park, Y.; Paul, A.; Prindle, C.; Ramachandran, R.; Sardesai, V.; Scholze, A.; Seo, S.; Southwick, R.; Strane, J.; Sun, X.; Tsutsui, G.; Tripathi, N.; Vega, R.; Weybright, M.; Xie, R.; Yeh, C.; Bu, H.; Burns, S.; Canaperi, D.; Celik, M.; Colburn, M.; Jagannathan, H.; Kanakasabaphthy, S.; Kleemeier, W.; Liebmann, L.; Mcherron, D.; Oldiges, P.; Paruchuri, V.; Spooner, T.; Stathis, J.; Divakaruni, R.; Gow, T.; Iacoponi, J.; Jenq, J.; Sampson, R; Yang, W.; Khare, M.;

2014 / IEEE


This item from - IEEE Conference - 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT) - In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.