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Impact of BTI on random logic circuit critical timing

By: Cheung, K.P.; Lu, J.W.; Jiao, G.F.; Vaz, C.; Ryan, J.T.; Campbell, J.P.;

2014 / IEEE

Description

This item from - IEEE Conference - 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT) - Using a newly developed single transistor eye-diagram method, we examined the effect of BTI stress on logic circuit critical timing under a realistic bit pattern (pseudo random). We demonstrated that the recoverable part of the BTI degradation produce significant timing skew that is random in nature. This random timing skew is in addition to the systematic timing degradation captured in measurements using ring oscillator circuits. The size of this random skew is very large and can be a serious problem for logic circuit under tight timing budget. This effect has not been known before and therefore not accounted for in any of the proposed circuit methodology to mitigate BTI effects.