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Cost-effective power delivery to support per-core voltage domains for power-constrained processors

By: Sinkar, A.A.; Ghasemi, H.R.; Nam Sung Kim; Schulte, M.J.;

2012 / IEEE / 978-1-4503-1199-1

Description

This item was taken from the IEEE Conference ' Cost-effective power delivery to support per-core voltage domains for power-constrained processors ' Per-core voltage domains can improve performance under a power constraint. Most commercial processors, however, only have one chip-wide voltage domain because splitting the voltage domain into per-core voltage domains and powering them with multiple off-chip voltage regulators (VRs) incurs a high cost for the platform and package designs. Although using on-chip switching VRs can be an alternative solution, integrating high-quality inductors and cores on the same chip has been a technical challenge. In this paper, we propose a cost-effective power delivery technique to support per-core voltage domains. Our technique is based on the observations that (i) core-to-core voltage variations are relatively small for most execution intervals when the voltages/frequencies are optimized to maximize performance under a power constraint and (ii) per-core power-gating devices augmented with small circuits can serve as low-cost VRs that can provide high efficiency in situations like (i). Our experimental results show that processors using our technique can achieve power efficiency as high as those using per-core on-chip switching VRs at much lower cost.