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A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs
By: Tachibana, F.; Kushida, K.; Hirabayashi, O.; Takeyama, Y.; Niki, Y.; Yabe, T.; Kawasumi, A.; Sasaki, S.;
2012 / IEEE / 978-1-4673-0849-6
This item was taken from the IEEE Conference ' A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs ' A variation tolerant sense amplifier timing generator which utilizes a statistical method is proposed. The circuit monitors all the bitline delays and generates the worst timing from the delay distribution. The proposed timing generators have been implemented in 28nm and 40nm SRAMs. The 47% access time reduction has been confirmed in measured results.
Variation Tolerant Sense Amplifier Timing Generator
Size 28 Nm
Random Access Memory
Ultralow Voltage Sram
Access Time Reduction
Size 40 Nm
Worst-case Timing-generation Scheme