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A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS

By: Sakurai, M.; Niitsu, K.; Kobayashi, H.; Yamaguchi, T.J.; Hirabayashi, D.; Harigai, N.;

2012 / IEEE / 978-1-4673-0772-7

Description

This item was taken from the IEEE Conference ' A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS ' This paper demonstrates a reference-free, high-resolution on-chip timing jitter measurement circuit. It combines a self-referenced clock and a cascaded time difference amplifier (TDA), which results in reference-free, high-resolution timing jitter measurement without sacrificing operational speed. The test chip was designed and fabricated in 65 nm CMOS. Measured results of the proposed circuit show the possibility of detecting a timing jitter of 1.61-ps RMS in 820 MHz clock with less than 4% error.